MC68HC711K4CFN4 Datasheet, PDF (44/80 Pages) Motorola, Inc – 8-Bit Microcontroller

OPT2 —System Configuration Options 2
Bit 7
6
5
LIRDV CWOM
—
RESET:
0
0
0
4
IRVNE
—
LIRDV—LIR Driven
Refer to 2 Operating Modes.
CWOM —Port C Wired-OR Mode
0 = Port C operates normally.
1 = Port C outputs are open-drain.
Bit 5 —Not implemented
Always read zero
IRVNE —Internal Read Visibility/Not E
Refer to 2 Operating Modes.
LSBF —SPI LSB First Enable
Refer to 8 Serial Peripheral Interface.
SPR2 —SPI Clock (SCK) Rate Select
Refer to 8 Serial Peripheral Interface.
XDV[1:0] —XOUT Clock Divide Select
Refer to 2 Operating Modes.
PORTD —Port D Data
Bit 7
6
—
—
RESET:
0
0
Alt. Pin
Func.:
—
—
5
4
PD5
PD4
I
I
SS
SCK
3
LSBF
0
3
PD3
I
MOSI
2
SPR2
0
2
PD2
I
MISO
1
XDV1
0
1
PD1
I
TxD
$0038
Bit 0
XDV0
0
$0008
Bit 0
PD0
I
RxD
DDRD —Data Direction Register for Port D
RESET:
Bit 7
—
0
6
5
4
—
DDD5 DDD4
0
0
0
3
DDD3
0
2
DDD2
0
1
DDD1
0
$0009
Bit 0
DDD0
0
Bits [7:6] — Not implemented
Always read zero
DDD[5:0] — Data Direction for Port D
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
NOTE
When the SPI system is in slave mode, DDD5 has no meaning nor effect. When
the SPI system is in master mode, DDD5 determines whether bit 5 of PORTD is an
error detect input (DDD5 = 0) or a general-purpose output (DDD5 = 1). If the SPI
system is enabled and expects any of bits [4:2] to be an input that bit will be an input
regardless of the state of the associated DDR bit. If any of bits [4:2] are expected
to be outputs that bit will be an output only if the associated DDR bit is set.
MOTOROLA
44
M68HC11 K Series
MC68HC11KTS/D