MC68HC711K4CFN4 Datasheet, PDF (57/80 Pages) Motorola, Inc – 8-Bit Microcontroller

SPCR —Serial Peripheral Control Register
$0028
RESET:
Bit 7
SPIE
0
6
SPE
0
5
DWOM
0
4
MSTR
0
3
CPOL
0
2
CPHA
1
1
SPR1
U
Bit 0
SPR0
U
SPIE —Serial Peripheral Interrupt Enable
0 = SPI interrupts disabled
1 = SPI interrupts enabled
SPE —Serial Peripheral System Enable
0 = SPI off
1 = SPI on
DWOM —Port D Wired-OR Mode Option for SPI Pins PD[5:2] (See also WOMS bit in SCCR1.)
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR —Master Mode Select
0 = Slave mode
1 = Master mode
CPOL, CPHA —Clock Polarity, Clock Phase
Refer to the following figure, SPI Transfer Format.
SCK CYCLE #
(FOR REFERENCE)
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE INPUT
(CPHA = 0) DATA OUT
SAMPLE INPUT
(CPHA = 1) DATA OUT
SS (TO SLAVE)
1
2
3
4
5
6
7
8
MSB
6
5
4
3
2
1
LSB
MSB
6
5
4
3
2
1
LSB
Figure 13 SPI Transfer Format
NOTE
This figure shows transmission order when LSBF = 0 default. If LSBF = 1, data is
transferred in reverse order (LSB first).
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
57