MC68HC711K4CFN4 Datasheet, PDF (30/80 Pages) Motorola, Inc – 8-Bit Microcontroller

Bit 7 — Not implemented
Always reads zero
MM1CR — Memory Mapping Window 1 Control Register
When a 64 Kbyte CPU address falls within window 1, the value in MM1CR is driven out from the corre-
sponding expansion address lines to enable the specified bank in the window.
MM2CR — Memory Mapping Window 2 Control Register
When a 64 Kbyte CPU address falls within window 2, the value in MM2CR is driven out from the corre-
sponding expansion address lines to enable the specified bank in the window.
Bit 0 — Not implemented
Always reads zero
4.2 Overlap Guidelines
• On-chip registers, RAM, and EEPROM are higher priority than expansion windows. If a window
overlaps RAM, registers, or EEPROM, they appear in all banks at their CPU address.
• If a window overlaps on-chip ROM/EPROM, the ROM/EPROM appears only in banks with
XA[18:16] = 0:0:0.
• Window 1 is higher priority than window 2, therefore any overlapped portion of window 2 is inac-
cessible.
4.3 Chip Selects
M68HC11 K-series MCUs have four software configured chip selects that are enabled in expanded
modes. The chip select for I/O (CSIO) is used for I/O expansion. The program chip select (CSPROG)
is used with an external memory that contains the reset vectors and program. The two general-purpose
chip selects, CSGP1 and CSGP2, are used to enable external devices. These external devices can be
in the 64 Kbyte memory space or in the expanded memory space. Chip select signals are a shared func-
tion of port H. When an MCU pin is not used for chip select functions it can be used for general-purpose
I/O. The following table contains a summary of the attributes of each chip select that can be controlled
by user software.
MOTOROLA
30
M68HC11 K Series
MC68HC11KTS/D