MC68HC711K4CFN4 Datasheet, PDF (29/80 Pages) Motorola, Inc – 8-Bit Microcontroller

W1SZ[1:0] —Window 1 Size
These bits select the size of memory expansion window 1.
WxSZ[1:0]
00
01
10
11
Window Size
Window disabled
8 K —Window can have up to 64 8-Kbyte banks
16 K —Window can have up to 32 16-Kbyte banks
32 K —Window can have up to 16 32-Kbyte banks
MMWBR — Memory Mapping Window Base
Bit 7
6
5
4
$0057 W2A15 W2A14 W2A13
—
RESET:
0
0
0
0
3
W1A15
0
2
W1A14
0
1
W1A13
0
$0057
Bit 0
—
0
W2A[15:13] —Window 2 Base Address
Selects the three most significant bit (MSB) of the base address for memory mapping window 2. Refer
to the table following W1A[15:13].
Bit 4 —Not implemented
Always reads zero
W1A[15:13] —Window Base 1 Address
Selects the three MSB of the base address for memory mapping window 1. Refer to the following table
for additional information.
MSB Bits
WxA[15:13]
000
001
010
011
100
101
110
111
8K
$0000
$2000
$4000
$6000
$8000
$A000
$C000
$E000
Window Base Address
16 K
32 K
$0000
$0000
$0000
$0000
$4000
$4000
$4000
$4000
$8000
$8000
$8000
$8000
$C000
$8000
$C000
$8000
Bit 0 —Not implemented
Always reads zero
NOTE
A special case exists when the bank size is 32 Kbytes and the window base ad-
dress is $4000. The XA14 signal connected to the ADDR14 pin of the memory de-
vice automatically drives an inverted CPU ADDR14 signal onto the XA14 pin when
the window is active. The effect occurs while the CPU address is in the $4000–
$BFFF range, the XA pins and external physical memory range is $0000–$7FFF.
MM1CR–MM2CR —Memory Mapping Window 1 and 2 Control
$0058
$0059
RESET:
Bit 7
—
—
0
6
X1A18
X2A18
0
5
X1A17
X2A17
0
4
X1A16
X2A16
0
3
X1A15
X2A15
0
2
X1A14
X2A14
0
1
X1A13
X2A13
0
$0058–$0059
Bit 0
—
—
0
MM1CR
MM2CR
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
29