MC68HC711K4CFN4 Datasheet, PDF (43/80 Pages) Motorola, Inc – 8-Bit Microcontroller

PORTB —Port B Data
$0004
Bit 7
6
5
4
3
2
1
Bit 0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
S. Chip or
Boot:
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
RESET:
I
I
I
I
I
I
I
I
Expan. or
Test: ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8
Reset state is mode dependent. In single-chip or bootstrap modes, port B pins are high-impedance in-
puts with selectable internal pull-up resistors. In expanded or test modes, port B pins are high order ad-
dress outputs and PORTB is not in the memory map.
DDRB —Data Direction Register for Port B
$0002
RESET:
Bit 7
DDB7
0
6
DDB6
0
5
DDB5
0
4
DDB4
0
3
DDB3
0
2
DDB2
0
1
DDB1
0
Bit 0
DDB0
0
DDB[7:0] —Data Direction for Port B
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
PORTC —Port C Data
$0006
Bit 7
6
5
4
3
2
1
Bit 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
S. Chip or
Boot:
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
RESET:
0
0
0
0
0
0
0
0
Expan. or
Test:
DATA7
DATA6
DATA5
DATA4 DATA3
DATA2
DATA1
DATA0
Reset state is mode dependent. In single-chip or bootstrap modes, port C pins are high-impedance in-
puts with selectable internal pull-up resistors. In expanded or test modes, port C pins are data bus inputs
and outputs and PORTC is not in the memory map. Refer to CWOM bit in OPT2 register description
that follows.
DDRC —Data Direction Register for Port C
$0007
RESET:
Bit 7
DDC7
0
6
DDC6
0
5
DDC5
0
4
DDC4
0
3
DDC3
0
2
DDC2
0
1
DDC1
0
Bit 0
DDC0
0
DDC[7:0] —Data Direction for Port C. Refer to CWOM bit in OPT2 register description that follows.
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
43