MC68HC711K4CFN4 Datasheet, PDF (28/80 Pages) Motorola, Inc – 8-Bit Microcontroller

Number of Banks
2
4
8
16
32
64
Table 5 CPU Address and Address Expansion Signals
8 Kbytes
Window Size
16 Kbytes
32 Kbytes
ADDR[12:0]
XA13
ADDR[12:0]
XA[14:13]
ADDR[12:0]
XA[15:13]
ADDR[12:0]
XA[16:13]
ADDR[12:0]
XA[17:13]
ADDR[12:0]
XA[18:13]
ADDR[13:0]
XA14
ADDR[13:0]
XA[15:14]
ADDR[13:0]
XA[16:14]
ADDR[13:0]
XA[17:14]
ADDR[13:0]
XA[18:14]
—
—
ADDR[14:0]
XA15
ADDR[14:0]
XA[16:15]
ADDR[14:0]
XA[17:15]
ADDR[14:0]
XA[18:15]
—
—
—
—
32 Kbytes
(Window Based at
$4000)
ADDR[13:0]
XA[15:14]
ADDR[13:0]
XA[16:14]
ADDR[13:0]
XA[17:14]
ADDR[13:0]
XA[18:14]
—
—
—
—
PGAR — Port G Assignment
Bit 7
6
—
—
RESET:
0
0
5
PGAR5
0
4
PGAR4
0
3
PGAR3
0
2
PGAR2
0
1
PGAR1
0
$002D
Bit 0
PGAR0
0
Bits [7:6] — Not implemented
Always read zero
PGAR[5:0] —Port G Pin Assignment Bits [5:0]
0 = Corresponding port G pin is general-purpose I/O
1 = Corresponding port G pin is address line, XA[18:13]
NOTE
A special case exists for expansion address lines XA[15:13] that overlap the CPU
address lines ADDR[15:13]. If these lines are selected as expansion address lines
in PGAR, but are not used in either window, the corresponding CPU address line
is output on the appropriate port G pin.
MMSIZ — Memory Mapping Size
Bit 7
6
5
4
3
MXGS2 MXGS1 W2SZ1 W2SZ0
—
RESET:
0
0
0
0
0
$0056
2
1
Bit 0
—
W1SZ1 W1SZ0
0
0
0
MXGS[2:1] — Memory Expansion Select for General-Purpose Chip Select 2 or 1
0 = General-purpose chip select 2 or 1 based on 64 Kbyte CPU address
1 = General-purpose chip select 2 or 1 based on expansion address
W2SZ[1:0] — Window 2 Size
These bits select the size of memory expansion window 2. Refer to the table following W1SZ[1:0].
Bits [3:2] — Not implemented
Always read zero
MOTOROLA
28
M68HC11 K Series
MC68HC11KTS/D