PIC24HJ12GP201_11 Datasheet, PDF (90/262 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers 5-cycle latency

PIC24HJ12GP201/202
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER^(1,3)
U-0
—
bit 15
R-0
R-0
R-0
U-0
R/W-y
COSC<2:0>
—
R/W-y
NOSC<2:0>⁽²⁾
R/W-y
bit 8
R/W-0
R/W-0
R-0
U-0
R/C-0
CLKLOCK IOLOCK
LOCK
—
CF
bit 7
U-0
R/W-0
R/W-0
—
LPOSCEN OSWEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
y = Value set from Configuration bits on POR
C = Clearable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC<2:0>: Current Oscillator Selection bits (read-only)
111 = Fast RC oscillator (FRC) with Divide-by-n
110 = Fast RC oscillator (FRC) with Divide-by-16
101 = Low-Power RC oscillator (LPRC)
100 = Secondary oscillator (SOSC)
011 = Primary oscillator (XT, HS, EC) with PLL
010 = Primary oscillator (XT, HS, EC)
001 = Fast RC oscillator (FRC) with Divide-by-n plus PLL
000 = Fast RC oscillator (FRC)
bit 11
bit 10-8
Unimplemented: Read as ‘0’
NOSC<2:0>: New Oscillator Selection bits⁽²⁾
111 = Fast RC oscillator (FRC) with Divide-by-n
110 = Fast RC oscillator (FRC) with Divide-by-16
101 = Low-Power RC oscillator (LPRC)
100 = Secondary oscillator (SOSC)
011 = Primary oscillator (XT, HS, EC) with PLL
010 = Primary oscillator (XT, HS, EC)
001 = Fast RC oscillator (FRC) with Divide-by-n plus PLL
000 = Fast RC oscillator (FRC)
bit 7
CLKLOCK: Clock Lock Enable bit
If clock switching is enabled and FSCM is disabled (FOSC<FCKSM> = 0b01)
1 = Clock switching is disabled, system clock source is locked
0 = Clock switching is enabled, system clock source can be modified by clock switching
bit 6
IOLOCK: Peripheral Pin Select Lock bit
1 = Peripherial Pin Select is locked, write to peripheral pin select register is not allowed
0 = Peripherial Pin Select is unlocked, write to peripheral pin select register is allowed
bit 5
LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied
0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
bit 4
Unimplemented: Read as ‘0’
Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70186) in the
“dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip web site) for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transition clock source between the two PLL modes.
3: This register is reset only on a Power-on Reset (POR).
DS70282E-page 90
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