PIC24HJ12GP201_11 Datasheet, PDF (169/262 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers 5-cycle latency

PIC24HJ12GP201/202
TABLE 19-2: PIC24HJ12GP201/202 CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
RTSP
Effect
Description
FWDTEN
WINDIS
WDTPRE
WDTPOST<3:0>
ALTI2C
FPWRT<2:0>
JTAGEN
ICS<1:0>
FWDT
FWDT
FWDT
FWDT
FPOR
FPOR
FICD
FICD
Immediate Watchdog Timer Enable bit
1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled.
Clearing the SWDTEN bit in the RCON register will have no effect.)
0 = Watchdog Timer enabled/disabled by user software (LPRC can be
disabled by clearing the SWDTEN bit in the RCON register)
Immediate Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
Immediate Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
Immediate Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
.
.
.
0001 = 1:2
0000 = 1:1
Immediate Alternate I²C™ pins
1 = I²C mapped to SDA1/SCL1 pins
0 = I²C mapped to ASDA1/ASCL1 pins
Immediate Power-on Reset Timer Value Select bits
111 = PWRT = 128 ms
110 = PWRT = 64 ms
101 = PWRT = 32 ms
100 = PWRT = 16 ms
011 = PWRT = 8 ms
010 = PWRT = 4 ms
001 = PWRT = 2 ms
000 = PWRT = Disabled
Immediate JTAG Enable bit
1 = JTAG enabled
0 = JTAG disabled
Immediate ICD Communication Channel Select bits
11 = Communicate on PGEC1 and PGED1
10 = Communicate on PGEC2 and PGED2
01 = Communicate on PGEC3 and PGED3
00 = Reserved, do not use
© 2007-2011 Microchip Technology Inc.
DS70282E-page 169