PIC24HJ12GP201_11 Datasheet, PDF (147/262 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers 5-cycle latency

PIC24HJ12GP201/202
17.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note 1: This data sheet summarizes the features
of the PIC24HJ12GP201/202 family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Section 17. UART”
(DS70188) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available in the PIC24HJ12GP201/202 device family.
The UART is a full-duplex asynchronous system that
can communicate with peripheral devices, such as
personal computers, LIN, and RS-232, and RS-485
interfaces. The module also supports a hardware flow
control option with the UxCTS and UxRTS pins and
also includes an IrDA^® encoder and decoder.
The primary features of the UART module are:
• Full-Duplex, 8-bit, or 9-bit Data Transmission
through the UxTX and UxRX pins
• Even, Odd, or No Parity options (for 8-bit data)
• One or two stop bits
• Hardware Flow Control Option with UxCTS and
UxRTS pins
• Fully Integrated Baud Rate Generator with 16-bit
prescaler
• Baud rates ranging from 10 Mbps to 38 bps at 40
MIPS
• 4-deep First-In First-Out (FIFO) Transmit Data
Buffer
• 4-Deep FIFO Receive Data Buffer
• Parity, framing and buffer overrun error detection
• Support for 9-bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive interrupts
• A separate interrupt for all UART error conditions
• Loopback mode for diagnostic support
• Support for Sync and Break characters
• Support for automatic baud rate detection
• IrDA^® encoder and decoder logic
• 16x baud clock output for IrDA^® support
A simplified block diagram of the UART module is
shown in Figure 17-1. The UART module consists of
these key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 17-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA^®
Hardware Flow Control
UART Receiver
UxRTS/BCLK
UxCTS
UxRX
UART Transmitter
UxTX
© 2007-2011 Microchip Technology Inc.
DS70282E-page 147