PIC24HJ12GP201_11 Datasheet, PDF (256/262 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers 5-cycle latency

PIC24HJ12GP201/202
Use with WDT ........................................................... 171
Internet Address................................................................ 259
Interrupt Control and Status Registers................................ 63
IECx ............................................................................ 63
IFSx............................................................................. 63
INTCON1 .................................................................... 63
INTCON2 .................................................................... 63
IPCx ............................................................................ 63
Interrupt Setup Procedures ................................................. 85
Initialization ................................................................. 85
Interrupt Disable.......................................................... 85
Interrupt Service Routine ............................................ 85
Trap Service Routine .................................................. 85
Interrupt Vector Table (IVT) ................................................ 59
Interrupts Coincident with Power Save Instructions............ 98
J
JTAG Boundary Scan Interface ........................................ 167
JTAG Interface .................................................................. 172
M
Memory Organization.......................................................... 25
Microchip Internet Web Site .............................................. 259
MPLAB ASM30 Assembler, Linker, Librarian ................... 184
MPLAB Integrated Development Environment Software .. 183
MPLAB PM3 Device Programmer..................................... 186
MPLAB REAL ICE In-Circuit Emulator System................. 185
MPLINK Object Linker/MPLIB Object Librarian ................ 184
Multi-Bit Data Shifter ........................................................... 24
N
NVM Module
Register Map............................................................... 38
O
Open-Drain Configuration ................................................. 102
Oscillator Configuration....................................................... 87
Output Compare................................................................ 129
Registers ................................................................... 131
P
Packaging ......................................................................... 231
Details ....................................................................... 233
Marking ............................................................. 231, 232
Peripheral Module Disable (PMD)....................................... 98
Peripheral Pin Select Module
Input Register Map...................................................... 34
Output Register Map for PIC24HJ12GP202 ............... 34
Pinout I/O Descriptions (table) ............................................ 11
PMD Module
Register Map............................................................... 38
PORTA
Register Map............................................................... 37
PORTB
Register Map for PIC24HJ12GP201 ........................... 37
Register Map for PIC24HJ12GP202 ........................... 37
Power-on Reset (POR) ....................................................... 56
Power-Saving Features....................................................... 97
Clock Frequency and Switching.................................. 97
Program Address Space ..................................................... 25
Construction ................................................................ 41
Data Access from Program Memory Using Program
Space Visibility.................................................... 44
Data Access from Program Memory Using Table Instruc-
tions .................................................................... 43
Data Access from, Address Generation...................... 42
DS70282E-page 256
Memory Map for PIC24HJ12GP201/202 .................... 25
Table Read Instructions
TBLRDH ............................................................. 43
TBLRDL.............................................................. 43
Visibility Operation ...................................................... 44
Program Memory
Interrupt Vector ........................................................... 26
Organization ............................................................... 26
Reset Vector ............................................................... 26
R
Reader Response............................................................. 260
Registers
AD1CHS0 (ADC1 Input Channel 0 Select ................ 164
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 161
AD1CON1 (ADC1 Control 1) .................................... 157
AD1CON2 (ADC1 Control 2) .................................... 159
AD1CON3 (ADC1 Control 3) .................................... 160
AD1CSSL (ADC1 Input Scan Select Low)................ 166
AD1PCFGL (ADC1 Port Configuration Low) ............ 166
CLKDIV (Clock Divisor) .............................................. 92
CORCON (Core Control) ...................................... 23, 65
I2CxCON (I2Cx Control) ........................................... 141
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 145
I2CxSTAT (I2Cx Status) ........................................... 143
ICxCON (Input Capture x Control)............................ 128
IEC0 (Interrupt Enable Control 0) ............................... 72
IEC1 (Interrupt Enable Control 0) ............................... 74
IEC4 (Interrupt Enable Control 0) ............................... 75
IFS0 (Interrupt Flag Status 0) ..................................... 68
IFS1 (Interrupt Flag Status 1) ..................................... 70
IFS4 (Interrupt Flag Status 4) ..................................... 71
INTCON1 (Interrupt Control 1).................................... 66
INTCON2 (Interrupt Control 2).................................... 67
INTTREG Interrupt Control and Status Register ........ 84
IPC0 (Interrupt Priority Control 0) ............................... 76
IPC1 (Interrupt Priority Control 1) ............................... 77
IPC16 (Interrupt Priority Control 16) ........................... 83
IPC2 (Interrupt Priority Control 2) ............................... 78
IPC3 (Interrupt Priority Control 3) ............................... 79
IPC4 (Interrupt Priority Control 4) ............................... 80
IPC5 (Interrupt Priority Control 5) ............................... 81
IPC7 (Interrupt Priority Control 7) ............................... 82
NVMCON (Flash Memory Control) ............................. 47
NVMKEY (Nonvolatile Memory Key) .......................... 48
OCxCON (Output Compare x Control) ..................... 131
OSCCON (Oscillator Control) ..................................... 90
OSCTUN (FRC Oscillator Tuning).............................. 94
PLLFBD (PLL Feedback Divisor)................................ 93
PMD1 (Peripheral Module Disable Control Register 1) ..
99
PMD2 (Peripheral Module Disable Control Register 2) ..
100
RCON (Reset Control)................................................ 52
SPIxCON1 (SPIx Control 1)...................................... 135
SPIxCON2 (SPIx Control 2)...................................... 137
SPIxSTAT (SPIx Status and Control) ....................... 134
SR (CPU Status)................................................... 22, 64
T1CON (Timer1 Control) .......................................... 120
T2CON Control ......................................................... 124
T3CON Control ......................................................... 125
UxMODE (UARTx Mode).......................................... 148
UxSTA (UARTx Status and Control)......................... 150
Reset
Illegal Opcode....................................................... 51, 57
Trap Conflict ............................................................... 57
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