PIC24HJ12GP201_11 Datasheet, PDF (25/262 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers 5-cycle latency

PIC24HJ12GP201/202
4.0 MEMORY ORGANIZATION
Note:
This data sheet summarizes the features
of the PIC24HJ12GP201/202 family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Section 4. Program
Memory” (DS70202) of the “dsPIC33F/
PIC24H Family Reference Manual”, which
is available from the Microchip website
(www.microchip.com).
The PIC24HJ12GP201/202 architecture features
separate program and data memory spaces and
buses. This architecture also allows the direct access
of program memory from the data space during code
execution.
4.1 Program Address Space
The program address memory space of the
PIC24HJ12GP201/202 devices is 4M instructions. The
space is addressable by a 24-bit value derived either
from the 23-bit Program Counter (PC) during program
execution, or from table operation or data space
remapping as described in Section 4.4 “Interfacing
Program and Data Memory Spaces”.
User application access to the program memory space is
restricted to the lower half of the address range (0x000000
to 0x7FFFFF). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to the
Configuration bits and Device ID sections of the
configuration memory space.
The memory map for the PIC24HJ12GP201/202 family of
devices is shown in Figure 4-1.
FIGURE 4-1:
PROGRAM MEMORY FOR PIC24HJ12GP201/202 DEVICES
PIC24HJ12GP201/202
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(4K instructions)
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x001FFE
0x002000
Unimplemented
(Read ‘0’s)
© 2007-2011 Microchip Technology Inc.
0x7FFFFE
0x800000
Reserved
Device Configuration
Registers
0xF7FFFE
0xF80000
0xF80017
0xF80018
Reserved
DEVID (2)
0xFEFFFE
0xFF0000
0xFFFFFE
DS70282E-page 25