PIC24HJ12GP201_11 Datasheet, PDF (56/262 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers 5-cycle latency

PIC24HJ12GP201/202
6.2 POR
A POR circuit ensures the device is reset from power-
on. The POR circuit is active until VDD crosses the
VPOR threshold and the delay TPOR has elapsed. The
delay TPOR ensures the internal device bias circuits
become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate
requirements to generate the POR. Refer to
Section 22.0 “Electrical Characteristics” for details.
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
FIGURE 6-3:
BROWN-OUT SITUATIONS
6.3 BOR and PWRT
The on-chip regulator has a BOR circuit that resets the
device when the VDD is too low (VDD < VBOR) for proper
device operation. The BOR circuit keeps the device in
Reset until VDD crosses VBOR threshold and the delay
TBOR has elapsed. The delay TBOR ensures the voltage
regulator output becomes stable.
The BOR status (BOR) bit in the Reset Control
(RCON<1>) register is set to indicate the Brown-out
Reset.
The device will not run at full speed after a BOR as the
VDD should rise to acceptable levels for full-speed
operation. The PWRT provides power-up time delay
(TPWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
The power-up timer delay (TPWRT) is programmed by
the Power-on Reset Timer Value Select
(FPWRT<2:0>) bits in the POR Configuration
(FPOR<2:0>) register, which provides eight settings
(from 0 ms to 128 ms). Refer to Section 19.0 “Special
Features” for further details.
Figure 6-3 shows the typical brown-out scenarios. The
Reset delay (TBOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point.
VDD
SYSRST
TBOR + TPWRT
VBOR
VDD
SYSRST
VDD dips before PWRT expires
VDD
SYSRST
TBOR + TPWRT
TBOR + TPWRT
VBOR
VBOR
DS70282E-page 56
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