PIC24HJ12GP201_11 Datasheet, PDF (105/262 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers 5-cycle latency

PIC24HJ12GP201/202
TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)
Function
RPnR<4:0>
Output Name
NULL
U1TX
U1RTS
SDO1
SCK1OUT
SS1OUT
OC1
OC2
00000
00011
00100
00111
01000
01001
10010
10011
RPn tied to default port pin
RPn tied to UART1 Transmit
RPn tied to UART1 Ready To Send
RPn tied to SPI1 Data Output
RPn tied to SPI1 Clock Output
RPn tied to SPI1 Slave Select Output
RPn tied to Output Compare 1
RPn tied to Output Compare 2
10.4.3 CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC24H devices include three features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
10.4.3.1 Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these
registers, they must be unlocked in hardware. The
register lock is controlled by the IOLOCK bit
(OSCCON<6>). Setting IOLOCK prevents writes to
the control registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1. Write 0x46 to OSCCON<7:0>.
2. Write 0x57 to OSCCON<7:0>.
3. Clear (or set) IOLOCK as a single operation.
Note:
MPLAB^® C30 provides built-in C
language functions for unlocking the
OSCCON register:
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
See MPLAB IDE Help for more
information.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the peripheral pin selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
10.4.3.2 Continuous State Monitoring
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a configuration mismatch Reset will
be triggered.
10.4.3.3 Configuration Bit Pin Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPINRx and RPORx registers. The IOL1WAY
(FOSC<5>) configuration bit blocks the IOLOCK bit
from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure will
not execute, and the peripheral pin select control regis-
ters cannot be written to. The only way to clear the bit
and re-enable peripheral remapping is to perform a
device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows user applications unlimited access
(with the proper use of the unlock sequence) to the
peripheral pin select registers.
10.5 Peripheral Pin Select Registers
The PIC24HJ12GP201/202 devices implement 17
registers for remappable peripheral configuration:
• Input Remappable Peripheral Registers (9)
• Output Remappable Peripheral Registers (8)
Note:
Input and Output Register values can only
be changed if OSCCON<IOLOCK> = 0.
See Section 10.4.3.1 “Control Register
Lock” for a specific command sequence.
© 2007-2011 Microchip Technology Inc.
DS70282E-page 105