PIC24HJ12GP201_11 Datasheet, PDF (58/262 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers 5-cycle latency

PIC24HJ12GP201/202
6.9.2
UNINITIALIZED W REGISTER
RESET
Any attempts to use the uninitialized W register as an
address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
Resets and is considered uninitialized until written to.
6.9.3 SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
branch instruction.
The VFC occurs when the Program Counter is
reloaded with an Interrupt or Trap vector.
Refer to Section 19.6 “Code Protection and
CodeGuard™ Security” for more information on
Security Reset.
6.10 Using the RCON Status Bits
The user application can read the Reset Control
(RCON) register after any device Reset to determine
the cause of the Reset.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
Table 6-3 provides a summary of Reset Flag Bit
operation.
TABLE 6-3: RESET FLAG BIT OPERATION
Flag Bit
Set by:
TRAPR (RCON<15>)
IOPWR (RCON<14>)
CM (RCON<9>)
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
Trap conflict event
Illegal opcode or uninitialized
W register access or Security Reset
Configuration Mismatch
MCLR Reset
RESET instruction
WDT Time-out
SLEEP (RCON<3>)
PWRSAV #SLEEP instruction
IDLE (RCON<2>)
PWRSAV #IDLE instruction
BOR (RCON<1>)
POR, BOR
POR (RCON<0>)
POR
Note: All Reset flag bits can be set or cleared by user software.
Cleared by:
POR, BOR
POR, BOR
POR, BOR
POR
POR, BOR
PWRSAV instruction,
CLRWDT instruction, POR, BOR
POR, BOR
POR, BOR
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DS70282E-page 58
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