PIC24HJ12GP201_11 Datasheet, PDF (246/262 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers 5-cycle latency

PIC24HJ12GP201/202
Revision C (May 2008)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
The major changes are referenced by their respective
section in the following table.
TABLE 23-1: MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, 16-Bit
Digital Signal Controllers”
Added SSOP to list of available 28-pin packages (see “Packaging:” and Table 1).
Added External Interrupts column to Remappable Peripherals in the Controller
Families table and Note 2 (see Table 1).
Section 1.0 “Device
Overview”
Section 3.0 “Memory
Organization”
Added Note 1 to all pin diagrams, which references RPn pin usage by remappable
peripherals (see “Pin Diagrams”).
Changed Capture Input pin names from IC0-IC1 to IC1-IC2 and updated description
for AVDD (see Table 1-1).
Updated Reset values for the following SFRs: IPC0, IPC2-IPC7, IPC16, and
INTTREG (see Table 3-4).
The following changes were made to the ADC1 Register Maps:
• Updated the bit range for AD1CON3 from ADCS<5:0> to ADCS<7:0>)
(see Table 3-14 and Table 3-15).
• Added Bit 6 (PCFG7) and Bit 7 (PCFG6) names to AD1PCFGL (Table 3-14).
• Added Bit 6 (CSS7) and Bit 7 (CSS6) names to AD1CSSL (see Table 3-14).
• Changed Bit 5 and Bit 4 in AD1CSSL to unimplemented (see Table 3-14).
Section 4.0 “Flash Program
Memory”
Section 5.0 “Resets”
Section 7.0 “Oscillator
Configuration”
Updated the Reset value for CLKDIV in the System Control Register Map
(see Table 3-19).
Updated Section 4.3 “Programming Operations” with programming time formula.
Entire section was replaced to maintain consistency with other PIC24H data sheets.
Removed the first sentence of the third clock source item (External Clock) in
Section 7.1.1.2 “Primary”
Updated the default bit values for DOZE and FRCDIV in the Clock Divisor Register
(see Register 7-2).
Section 8.0 “Power-Saving
Features”
Section 9.0 “I/O Ports”
Added the center frequency in the OSCTUN register for the FRC Tuning bits
(TUN<5:0>) value 011111 and updated the center frequency for bits value 011110
(see Register 7-4)
Added the following two registers:
• PMD1: Peripheral Module Disable Control Register 1
• PMD2: Peripheral Module Disable Control Register 2
Added paragraph and Table 9-1 to Section 9.1.1 “Open-Drain Configuration”,
which provides details on I/O pins and their functionality.
Section 13.0 “Output
Compare”
Removed the following sections, which are now available in the related section of
the “PIC24H Family Reference Manual”:
• 9.4.2 “Available Peripherals”
• 9.4.3.3 “Mapping”
• 9.4.5 “Considerations for Peripheral Pin Selection”
Replaced sections 13.1, 13.2, and 13.3 and related figures and tables with entirely
new content.
DS70282E-page 246
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