PIC24HJ12GP201_11 Datasheet, PDF (172/262 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers 5-cycle latency

PIC24HJ12GP201/202
19.5 JTAG Interface
PIC24HJ12GP201/202 devices implement a JTAG
interface, which supports boundary scan device test-
ing, as well as in-circuit programming. Detailed infor-
mation on this interface will be provided in future
revisions of the document.
19.6 Code Protection and
CodeGuard™ Security
The PIC24HJ12GP201/202 devices offer the
intermediate implementation of CodeGuard Security.
CodeGuard Security enables multiple parties to
securely share resources (memory, interrupts and
peripherals) on a single chip. This feature helps protect
individual intellectual property in collaborative system
designs.
When coupled with software encryption libraries, Code-
Guard Security can be used to securely update Flash
even when multiple IPs reside on the single chip.
The code protection features are controlled by the
Configuration registers: FBS and FGS. The Secure
Segment and RAM is not implemented.
TABLE 19-3: CODE FLASH SECURITY
SEGMENT SIZES FOR 12 KB
DEVICES
CONFIG BITS
BSS<2:0> = x11
0K
VS = 256 IW
GS = 3840 IW
000000h
0001FEh
000200h
0003FEh
000400h
0007FEh
000800h
000FFEh
001000h
001FFEh
BSS<2:0> = x10
256
VS = 256 IW
BS = 256 IW
GS = 3584 IW
000000h
0001FEh
000200h
0003FEh
000400h
0007FEh
000800h
000FFEh
001000h
001FFEh
BSS<2:0> = x01
768
VS = 256 IW
BS = 768 IW
GS = 3072 IW
000000h
0001FEh
000200h
0003FEh
000400h
0007FEh
000800h
000FFEh
001000h
001FFEh
BSS<2:0> = x00
1792
VS = 256 IW
BS = 1792 IW
GS = 2048 IW
000000h
0001FEh
000200h
0003FEh
000400h
0007FEh
000800h
000FFEh
001000h
001FFEh
Note:
Refer to Section 23. “CodeGuard™
Security” (DS70199) of the “dsPIC33F/
PIC24H Family Reference Manual” for fur-
ther information on usage, configuration
and operation of CodeGuard Security.
DS70282E-page 172
© 2007-2011 Microchip Technology Inc.