PIC24HJ12GP201_11 Datasheet, PDF (127/262 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers 5-cycle latency

PIC24HJ12GP201/202
13.0 INPUT CAPTURE
Note 1: This data sheet summarizes the features
of the PIC24HJ12GP201/202 family of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 12. Input Capture”
(DS70198) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Input Capture module is useful in applications
requiring frequency (period) and pulse measurement.
The PIC24HJ12GP201/202 devices support up to eight
input capture channels.
The Input Capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
• Simple Capture Event modes:
- Capture timer value on every falling edge of
input at ICx pin
- Capture timer value on every rising edge of
input at ICx pin
• Capture timer value on every edge (rising and
falling)
• Prescaler Capture Event modes:
- Capture timer value on every 4th rising edge
of input at ICx pin
- Capture timer value on every 16th rising
edge of input at ICx pin
Each Input Capture channel can select one of two
16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or
external clock.
Other operational features include:
• Device wake-up from capture pin during CPU
Sleep and Idle modes
• Interrupt on Input Capture event
• 4-word FIFO buffer for capture values
- Interrupt optionally generated after 1, 2, 3, or
4 buffer locations are filled
• Use of Input Capture to provide additional
sources of external interrupts
FIGURE 13-1:
INPUT CAPTURE BLOCK DIAGRAM
From 16-bit Timers
TMR2 TMR3
ICx Pin
Prescaler
Counter
(1, 4, 16)
Edge Detection Logic
and
Clock Synchronizer
3
ICM<2:0> (ICxCON<2:0>)
Mode Select
ICOV, ICBNE (ICxCON<4:3>)
ICxI<1:0>
ICxCON
FIFO
R/W
Logic
Interrupt
Logic
16 ¹⁶
1
0
ICTMR
(ICxCON<7>)
ICxBUF
System Bus
Set Flag ICxIF
(in IFSn Register)
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
© 2007-2011 Microchip Technology Inc.
DS70282E-page 127