PIC24HJ12GP201_11 Datasheet, PDF (130/262 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers 5-cycle latency

PIC24HJ12GP201/202
14.1 Output Compare Modes
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare Control (OCxCON<2:0>) register.
Table 14-1 lists the different bit settings for the Output
Compare modes. Figure 14-2 illustrates the output
compare operation for various modes. The user
application must disable the associated timer when
writing to the output compare control registers to avoid
malfunctions.
Note:
See Section 13. “Output Compare” in
the “dsPIC33F/PIC24H Family Reference
Manual” (DS70209) for OCxR and
OCxRS register restrictions.
TABLE 14-1: OUTPUT COMPARE MODES
OCM<2:0>
Mode
OCx Pin Initial State
000 Module Disabled
Controlled by GPIO register
001 Active-Low One-Shot
0
010 Active-High One-Shot
1
011 Toggle Mode
Current output is maintained
100 Delayed One-Shot
0
101 Continuous Pulse mode
0
110 PWM mode without fault
protection
0, if OCxR is zero
1, if OCxR is non-zero
111 PWM mode with fault protection 0, if OCxR is zero
1, if OCxR is non-zero
OCx Interrupt Generation
—
OCx Rising edge
OCx Falling edge
OCx Rising and Falling edge
OCx Falling edge
OCx Falling edge
No interrupt
OCFA Falling edge for OC1 to OC4
FIGURE 14-2:
OUTPUT COMPARE OPERATION
Output Compare
Mode enabled
Timer is reset on
period match
OCxRS
TMRy
OCxR
Active Low One-Shot
(OCM = 001)
Active High One-Shot
(OCM = 010)
Toggle Mode
(OCM = 011)
Delayed One-Shot
(OCM = 100)
Continuous Pulse Mode
(OCM = 101)
PWM Mode
(OCM = 110 or 111)
DS70282E-page 130
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