PIC24HJ12GP201_11 Datasheet, PDF (65/262 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers 5-cycle latency

PIC24HJ12GP201/202
REGISTER 7-2: CORCON: CORE CONTROL REGISTER⁽¹⁾
U-0
—
bit 15
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
—
—
bit 8
U-0
—
bit 7
U-0
U-0
U-0
R/C-0
R/W-0
U-0
U-0
—
—
—
IPL3⁽²⁾
PSV
—
—
bit 0
Legend:
R = Readable bit
0’ = Bit is cleared
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 3
IPL3: CPU Interrupt Priority Level Status bit 3⁽²⁾
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
Note 1: For complete register details, see Register 3-2: “CORCON: Core Control Register”.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
© 2007-2011 Microchip Technology Inc.
DS70282E-page 65