PIC24HJ12GP201_11 Datasheet, PDF (40/262 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers 5-cycle latency

PIC24HJ12GP201/202
TABLE 4-22: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
Description
File Register Direct
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the Effective Address (EA.)
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
(Register Indexed)
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.
4.3.3 MOVE (MOV) INSTRUCTIONS
Move instructions provide a greater degree of
addressing flexibility than other instructions. In addition
to the addressing modes supported by most MCU
instructions, MOV instructions also support Register
Indirect with Register Offset Addressing mode, also
referred to as Register Indexed mode.
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (Register Offset)
field is shared by both source and
destination (but typically only used by
one).
In summary, the following addressing modes are
supported by move instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• 16-bit Literal
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
4.3.4 OTHER INSTRUCTIONS
In addition to the addressing modes outlined
previously, some instructions use literal constants of
various sizes. For example, BRA (branch) instructions
use 16-bit signed literals to specify the branch
destination directly, whereas the DISI instruction uses
a 14-bit unsigned literal field. In some instructions, such
as ADD Acc, the source of an operand or result is
implied by the opcode itself. Certain operations, such
as NOP, do not have any operands.
DS70282E-page 40
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