MRF89XAM8A-I Datasheet, PDF (88/140 Pages) Microchip Technology – Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver

MRF89XA
3.11.6
HOST MICROCONTROLLER
INTERFACE CONNECTIONS IN
PACKET MODE
Depending on the application, some of the host
microcontroller connections may not be needed:
• IRQ0: If none of the relevant IRQ sources are
used. In this case, leave the pin floating.
• IRQ1: If none of the relevant IRQ sources are
used. In this case, leave the pin floating.
• SDO: If no read register access is needed and the
device is used in TX mode only. In this case, pull
up to VDD through a 100 kΩ resistor.
Note:
The DATA pin (pin 20), which is unused in
Packet mode, should be pulled-up to VDD
through a 100 kΩ resistor. Table 2-4, pro-
vides details about MRF89XA pin configu-
ration and chip mode.
FIGURE 3-32:
HOST MCU
CONNECTIONS IN
PACKET MODE
MRF89XA
IRQ0
IRQ1
CSCON
CSDAT
SCK
SDI
SDO
PIC^®
Microcontroller
3.11.7 PACKET MODE EXAMPLE
The data processing related registers are appropriately
configured as shown in Table 3-13. In this example we
assume CRC is enabled with autoclear on.
TABLE 3-13: CONFIGURATION REGISTERS RELATED TO DATA PROCESSING (ONLY) IN
PACKET MODE
Register Name
Register Bits
TX RX
Description
DMODREG
DMODE0, DMODE1 X
FIFOCREG
FSIZE<1:0>
X
FIFOCREG
FTINT<5:0>
X
FTXRXIREG
IRQ0RXS<1:0>
—
FTXRXIREG
IRQ1RXS<1:0>
—
FTXRXIREG
IRQ1TX
X
FTPRIREG
IRQ0TXST
X
SYNCREG
SYNCREN
—
SYNCREG
SYNCWSZ<1:0>
—
SYNCREG
SYNCTEN<1:0>
—
SYNCV31REG
SYNCV<31:24>
—
SYNCV23REG
SYNCV<23:16>
—
SYNCV15REG
SYNCV<15:8>
—
SYNCV07REG
SYNCV<7:0>
—
PLOADREG
PLOADREG
MCHSTREN
X
PLDPLEN<6:0>
X⁽¹⁾
NADDSREG
NLADDR<7:0>
—
PKTCREG
PKTLENF
X
PKTCREG
PRESIZE<1:0>
X
PKTCREG
WHITEON
X
PKTCREG
CRCEN
X
PKTCREG
ADDFIL<1:0>
—
PKTCREG
CRCSTSEN
X
FCRCERG
ACFCRC
—
FCRCERG
FRWAXS
X
Note 1: Fixed format only.
X Defines data operation mode (ÆPacket)
X Defines FIFO size
X Defines FIFO threshold
X Defines IRQ0 source in RX & Stand-by modes
X Defines IRQ1 source in RX & Stand-by modes
— Defines IRQ1 source in TX mode
— Defines IRQ0 source in TX mode
X Enables Sync word recognition
X Defines Sync word size
X Defines the error tolerance on Sync word recognition
X Defines Sync word value
X Defines Sync word value
X Defines Sync word value
X Defines Sync word value
X Enables Manchester encoding/decoding
X Length in fixed format, max RX length in variable format
X Defines node address for RX address filtering
X Defines packet format (fixed or variable length)
— Defines the size of preamble to be transmitted
X Enables whitening/de-whitening process
X Enables CRC calculation/check
X Enables and defines address filtering
X Enables CRC Status check
X Enables FIFO autoclear if CRC failed
X Defines FIFO access in Stand-by mode
DS70622C-page 88
Preliminary
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