MRF89XAM8A-I Datasheet, PDF (40/140 Pages) Microchip Technology – Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver

MRF89XA
2.15.2
FIFO TRANSMIT PLL AND RSSI
INTERRUPT REQUEST
CONFIGURATION REGISTER
DETAILS
REGISTER 2-15: FTPRIREG: FIFO TRANSMIT PLL AND RSSI INTERRUPT REQUEST
CONFIGURATION REGISTER (ADDRESS:0x0E) (POR:0x01)
R/W-0
R/W-0
R/W-0
R/W-0
r
R/W-0
R/W-0
FIFOFM FIFOFSC TXDONE IRQ0TXST
—
RIRQS
LSTSPLL
bit 7
R/W-1
LENPLL
bit 0
R = Readable bit
-n = Value at POR
r = Reserved
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
FIFOFM: FIFO Filling Method bits
This bit decides the method of filling FIFO (supports Buffer mode only)
1 = Manually controlled by FIFO fill
0 = Automatically starts when a sync word is detected (default)
bit 6
FIFOFSC: FIFO Filling Status or Control bits
This bit indicate the status of FIFO filling and also controls the filling up of FIFO
(supports Buffer Mode only)
STATUS: Reading (FIFOFM = 0)
1 = FIFO getting filled (Î sync word has been detected)
0 = FIFO filling completed / stopped
CONTROL: Writing (FIFOFM = 1), clears the bit and waits for a new sync word (FOVRCLR = 0)
1 = Start filling the FIFO
0 = Stop filling the FIFO
bit 5
TXDONE: Transmit Done bit
This bit selects and IRQ source.
1 = TXDONE (goes high when the last bit has left the shift register).
0 = TX still in process
bit 4
IRQ0TXST: Transmit Start with IRQ0 bit
This bit indicates transmit start condition with IRQ0 as source.
If DMODE1:DMODE0 = 01 Î Buffer Mode:
1 = Transmit starts if FIFO is not empty, IRQ0 mapped to FIFOEMPTY
0 = Transmit starts if FIFO is full, IRQ0 mapped to FIFOEMPTY (default)
If DMODE1:DMODE0 = 1x Î Packet Mode:
1 = Transmit starts if FIFO is not empty, IRQ0 mapped to FIFOEMPTY
0 = Start transmission when the number of bytes in FIFO is greater than or equal to threshold set by
the FTINT<5:0> bits (FIFOCREG<5:0), IRQ0 mapped to FIFO_THRESHOLD
bit 3
Reserved: Reserved bit
1 = Set bit to ‘1’ (required)⁽¹⁾
0 = Reserved (default)
bit 2
RIRQS: RSSI IRQ Source
This bit indicates IRQ source as RSSI
1 = Detected signal is above the value determined by the RTIVAL<7:0> bits (RSTHIREG<7:0>)
0 = Detected signal is less than the value determined by the RTIVAL<7:0> bits (RSTHIREG<7:0>)
Writing a ‘1’ for this bit clears RIRQS.
Note 1: Setting this bit to ‘0’ disables the RSSI IRQ source. It can be left enabled at any time, and the user can
choose to map this interrupt to IRQ0/IRQ1 or not.
DS70622C-page 40
Preliminary
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