MRF89XAM8A-I Datasheet, PDF (21/140 Pages) Microchip Technology – Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver

MRF89XA
2.10 Receiver
The receiver is based on a superheterodyne
architecture and comprises the following major blocks:
• An LNA that provides low-noise RF gain followed
by an RF band-pass filter.
• A first mixer, which down-converts the RF signal
to an intermediate frequency equal to one-ninth of
the carrier frequency (f_rf 100 MHz for 915 MHz
signals).
• A variable gain first-IF preamplifier followed by
two second mixers, which down-convert the first
IF signal to I and Q signals at a low frequency
(zero-IF for FSK, low-IF for OOK).
• A two-stage IF filter followed by an amplifier chain
are available for both I and Q channels. Limiters
at the end of each chain drive the I and Q inputs
to the FSK demodulator function. An RSSI signal
is also derived from the I and Q IF amplifiers to
drive the OOK detector. The second filter stage in
each channel can be configured as either a third-
order Butterworth low-pass filter for FSK opera-
tion or an image reject polyphase band-pass filter
for OOK operation.
• An FSK arctangent type demodulator driven from
the I and Q limiter outputs, and an OOK demodu-
lator driven by the RSSI signal. Either detector
can drive a data and clock recovery function that
provides matched filter enhancement of the
demodulated data.
2.10.1 RECEIVER ARCHITECTURE
Figure 2-8 illustrates the receiver architecture block
diagram. The first IF is one-ninth of the RF frequency
(approximately 100 MHz). The second down-
conversion down-converts the I and Q signals to
baseband in the case of the FSK receiver (zero-IF) and
to a low-IF (IF2) for the OOK receiver.
After the second down-conversion stage, the received
signal is channel-select filtered and amplified to a level
adequate for demodulation. Both FSK and OOK
demodulation are available. Finally, an optional bit
synchronizer (BitSync) is provided to supply a
synchronous clock and data stream to a companion
microcontroller in Continuous mode, or to fill the FIFO
buffers with glitch-free data in Buffered mode.
Note: Image rejection is achieved using a SAW
filter on the RF input.
FIGURE 2-8:
RECEIVER ARCHITECTURE BLOCK DIAGRAM
First
down-conversion
Second
down-conversion
RSSI
OOK
Demod
LNA
LO2 RX
FSK
Demod
BitSync
Control Logic
- Pattern Recognition
- FIFO Handler
- SPI Interface
- Packet Handler
LO1 RX
RF
IF1
Baseband, IF2 in OOK
© 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 21