MRF89XAM8A-I Datasheet, PDF (53/140 Pages) Microchip Technology – Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver

MRF89XA
2.20.4 FIFO CRC CONFIGURATION
REGISTER DETAILS
REGISTER 2-32: FCRCREG: FIFO CRC CONFIGURATION REGISTER
(ADDRESS:0xIF) (POR:0x00)
R/W-0
R/W-0
r
r
r
r
r
ACFCRC FRWAXS
—
—
—
—
—
bit 7
r
—
bit 0
R = Readable bit
-n = Value at POR
r = Reserved
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-0
ACFCRC: Auto Clear FIFO CRC bit
This bit when enabled auto clears FIFO if CRC failed for the current packet.
1 = Disabled
0 = Enabled (default)
FRWAXS: FIFO Read/Write Access bit
This bit indicate the read/write access for FIFO in Stand-by mode.
1 = Read
0 = Write (default)
Reserved<5:0>: Reserved bits; do not use
00000 = Reserved (default)
DS70622C-page 53
Preliminary
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