MRF89XAM8A-I Datasheet, PDF (26/140 Pages) Microchip Technology – Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver

MRF89XA
2.12 FIFO and Shift Register (SR)
In Buffered and Packet modes of operation, data to be
transmitted and data that has been received are stored
in a configurable First In First Out (FIFO) buffer. The
FIFO is accessed through the SPI data interface and
provides several interrupts for transfer management.
The FIFO is 1 byte (8 bits) wide; therefore, it only
performs byte (parallel) operations, whereas the
demodulator functions serially. A shift register (SR) is
therefore employed to interface the demodulator and
the FIFO. In Transmit mode it takes bytes from the
FIFO and outputs them serially (MSB first) at the
programmed bit rate to the modulator. Similarly, in
Receive mode the shift register gets bit-by-bit data from
the demodulator and writes them byte-by-byte to the
FIFO. This is illustrated in Figure 2-16.
FIGURE 2-16:
FIFO AND SHIFT
REGISTER
2.13 MRF89XA Configuration, Control
and Status Registers
The memory in the MRF89XA transceiver is
implemented as static RAM and is accessible through
the SPI port. The memory configuration of the
MRF89XA is illustrated in Figure 2-17 and Figure 2-18.
Data TX/RX
1
MSB
Byte 1
Byte 0
8
SR (8 bits)
FIFO
LSB
FIGURE 2-17:
MRF89XA MEMORY SPACE
0x00
0x1F
Control Registers
0x00
0x40
Transmit/Receive
FIFO
64 bytes
Data TX/RX
1
SHIFT REGISTER
(8 bits)
MSB
DS70622C-page 26
Preliminary
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