MRF89XAM8A-I Datasheet, PDF (25/140 Pages) Microchip Technology – Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver

MRF89XA
2.11.2 SPI DATA
Write Byte (before/during TX) - To write bytes into the
FIFO, the timing diagram illustrated in Figure 2-14
should be followed by the host microcontroller.
Note:
It is compulsory to toggle CSDAT back
high between each byte written. The byte
is pushed into the FIFO on the rising edge
of CSDAT.
FIGURE 2-14:
WRITE BYTES SEQUENCE (EXAMPLE DIAGRAM FOR 2 BYTES)
12345678
12345678
CSDAT(In)
SCK (In)
SDI (In)
1stbyte written
D1(7) D1(6) D1(5) D1(4) D1(3)D1(2) D1(1) D1(0)
x
2ndbyte written
D2(7) D2(6) D2(5) D2(4) D2(3) D2(2) D2(1) D2(0)
SDO (Out)HZ
x
(input)
xxxxxxx
HZ
x
(input)
x
x
x
x
x
x
x x _HZ
(input)
Read Byte (after/during RX) - To read bytes from the
FIFO, the timing diagram illustrated in Figure 2-15
should be followed by the host microcontroller.
Note: It is recommended to toggle CSDAT back
high between each byte read.
FIGURE 2-15:
READ BYTES SEQUENCE (EXAMPLE DIAGRAM FOR 2 BYTES)
12345678
12345678
CSDAT (In)
SCK (In)
SDI (In)
xx x
xxxxxx
First byte read
xx x
xx x x x
Second byte read
SDO (Out)HZ D1(7) D1(6) D1(5) D1(4) D1(3) D1(2) D1(1) D1(0) HZ D2(7) D2(6) D2(5) D2(4) D2(3) D2(2) D2(1) D2(0) HZ
(input)
(input)
(input)
© 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 25