MRF89XAM8A-I Datasheet, PDF (27/140 Pages) Microchip Technology – Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver

MRF89XA
FIGURE 2-18:
MRF89XA REGISTERS MEMORY MAP
Register Name
0x00
GCONREG
Register Name
0x10
FILCREG
0x01
DMODREG
0x11
PFCREG
0x02
FDEVREG
0x12
SYNCREG
0x03
BRSREG
0x13
RSTSREG
0x04
FLTHREG
0x14
RSVREG
0x05
FIFOCREG
0x15
OOKCREG
0x06
R1CREG
0x16 SYNCV31REG
0x07
P1CREG
0x17 SYNCV23REG
0x08
S1CREG
0x18 SYNCV15REG
0x09
0x0A
R2CREG
P2CREG
0x19 _SYNCV07REG
0x1A
TXCONREG
0x0B
S2CREG
0x1B
CLKOREG
0x0C
PACREG
0x1C PLOADREG
0x0D FTXRXIREG
0x1D NADDSREG
0x0E
FTPRIREG
0x1E
PKTCREG
0x0F
RSTHIREG
0x1F
FCRCREG
The MRF89XA registers functionally handles
command, configuration, control, status or data/FIFO
fields as listed in Table 2-6. The registers operate on
parameters common to transmit and receive modes,
Interrupts, Sync pattern, crystal oscillator and packets.
The FIFO serves as a buffer for data transmission and
reception. There is a shifted register (SR) to handle bit
shifts for the FIFO during transmission and reception.
POR sets default values in all Configuration/Control/
Status registers.
© 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 27