MRF89XAM8A-I Datasheet, PDF (56/140 Pages) Microchip Technology – Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver

MRF89XA
3.1 Reset of the Chip
A power-on Reset of the MRF89XA is triggered at
power up. Additionally, a manual reset can be issued
by controlling the TEST8 pin (pin 13).
3.1.1 POWER-ON RESET (POR)
If the application requires the disconnection of VDD
from the MRF89XA, the user should wait for 10 ms
from the end of the POR cycle before commencing
communications using SPI. The TEST8 pin should be
left floating during the POR sequence. Figure 3-2
illustrates the POR Timing.
Note: Any CLKOUT-related activity can also be
used to detect that the chip is ready.
3.1.2 MANUAL RESET
A manual reset of the MRF89XA is possible even for
applications in which VDD cannot be physically
disconnected. The TEST8 pin should be pulled high for
100 µs and then released. The user should then wait 5
ms before using the chip. The pin is driven with an
open-drain output, and therefore, is pulled high while
the device is in POR. Figure 3-3 illustrates the Manual
Reset Timing
Note:
When the TEST8 pin is driven high, an
current consumption of up to 10 mA can
be seen on VDD.
FIGURE 3-2:
POR TIMING DIAGRAM
VDD
Pin 13
(output)
Undefined
Wait for
10 ms
Chip is ready from this point forward
FIGURE 3-3:
MANUAL RESET TIMING DIAGRAM
VDD
Pin 13
(input)
> 100 µs
High-Z
1
Wait for
5 ms
High-Z
Chip is ready from this point forward
DS70622C-page 56
Preliminary
© 2010–2011 Microchip Technology Inc.