MRF89XAM8A-I Datasheet, PDF (52/140 Pages) Microchip Technology – Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver

MRF89XA
2.20.3 PACKET CONFIGURATION
REGISTER DETAILS
REGISTER 2-31: PKTCREG: PACKET CONFIGURATION REGISTER
(ADDRESS:0x1E) (POR:0x48)
R/W-0
R/W-1
R/W-1
R/W-0
R/W-1
R/W-0
R/W-0
PKTLENF
PRESIZE<1:0>
WHITEON CHKCRCEN
ADDFIL<1:0>
bit 7
R/W-0
STSCRCEN
bit 0
R = Readable bit
-n = Value at POR
r = Reserved
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6-5
bit 4
bit 3
bit 2-1
bit 0
PKTLENF: Packet Length Format bit
1 = Variable Length Format
0 = Fixed Length Format (default)
PRESIZE<1:0>: Preamble Size bits
These bits indicate the size of the preamble bits to be transmitted.
11 = 4 bytes
10 = 3 bytes (default)
01 = 2 bytes
00 = 1 byte
WHITEON: Whitening/Dewhitening Process Enable bit
1 = ON
0 = OFF (default)
CHKCRCEN: Check (or Calculation) CRC Enable bit
1 = ON (default)
0 = OFF
ADDFIL<1:0>: Address Filtering bits
These bits determine the mode of filter out the addresses of received packet
11 = Node Address & 0x00 & 0xFF Accepted; otherwise, rejected
10 = Node Address & 0x00 Accepted; otherwise, rejected
01 = Node Address Accepted; otherwise, rejected
00 = OFF (default)
STSCRCEN: Status Check CRC Enable bit
This bit checks the status/result of the CRC of the current packet (read-only).
1 = OK
0 = Not OK
© 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 52