MRF89XAM8A-I Datasheet, PDF (77/140 Pages) Microchip Technology – Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver

MRF89XA
3.10 Buffered Mode
In Buffered mode operation the NRZ data to/from the
modulator or demodulator is not accessed by the host
microcontroller but is stored in the FIFO and accessed
via the SPI data interface. This frees the host
microcontroller for other tasks between processing
data from the MRF89XA. In addition, it simplifies
software development overhead and reduces
microcontroller performance requirements (i.e., speed,
response). Note that in this mode the packet handler
stays inactive. The interface for Buffer mode is shown
in Figure 3-21.
An important feature is also the ability to empty the
FIFO in Stand-by mode, ensuring low-power
consumption and adding greater software flexibility.
Note:
In this case Bit Synchronizer is automati-
cally enabled in Buffered mode. The Sync
word recognition must be enabled
(SYNCREN = 1) independently of the
FIFO filling method selected (FIFOFM).
3.10.1 TX PROCESSING
After entering TX in Buffered mode, the MRF89XA
expects the host microcontroller to write to the FIFO,
through the SPI data interface, and all the data bytes to
be transmitted (preamble, Sync word, payload).
Actual transmission of the first byte will start either
when the FIFO is not empty (that is, first byte written by
the host microcontroller) or when the FIFO is full
depending on the IRQ0TXST bit (FTPRIREG<4>) set-
ting.
In Buffered mode the packet length is not limited, as
long as there are bytes inside the FIFO to be sent. When
the last byte is transferred to the SR, the FIFOEMPTY
IRQ source is issued to interrupt the host
microcontroller, when the FIFO can still be filled with
additional bytes if required.
When the last bit of the last byte has left the Shift
Register (SR) (i.e, eight bit periods later), the TXDONE
interrupt source is issued and the user can exit TX
mode after waiting at least one bit period from the last
bit processed by the modulator. If the transmitter is
switched OFF during transmission (for example,
entering another chip mode), it will stop immediately,
even if there is still unsent data.
FIGURE 3-21:
BUFFERED MODE BLOCK DIAGRAM
MRF89XA
Control
IRQ0
IRQ1
Data
RX _SYNC
Recognition
TX
FIFO
(+SR)
SPI
CONFIG
DATA
CSCON
CSDAT
SCK
SDI
SDO
Datapath
© 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 77