MRF89XAM8A-I Datasheet, PDF (15/140 Pages) Microchip Technology – Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver

2.2 Reset Pin
The device enters the Reset mode if any of the
following events take place:
• Power-on Reset (POR)
• Manual Reset
The POR happens when the MRF89XA is switched on
using VDD. The POR cycle takes at least 10 ms to
execute any communication operations on the SPI bus.
An external hardware or manual Reset of the
MRF89XA can be performed by asserting the TEST8
pin (pin 13) to high for 100 µs and then releasing the
pin. After releasing the pin, it takes more than 5 ms for
the transceiver to be ready for any operations. The pin
is driven with an open-drain output, therefore, is pulled
high while the device is in POR. The device will not
accept commands during the Reset period. For more
information, refer to Section 3.1.2, Manual Reset.
2.3 RFIO Pin
The receiver and the transmitter share the same RFIO
pin (pin 31). Figure 2-3 illustrates the configuration of
the common RF front-end.
• In Transmit mode, the PA and the PA regulator
are ON with voltage on the PARS pin (pin 29)
equal to the nominal voltage of the regulator
(about 1.8V). The external RF choke inductance
is used to bias the PA.
• In Receive mode, the PA and PA regulator are
OFF and PARS is tied to ground. The external RF
choke inductor is used for biasing and matching
the LNA (this is basically implemented as a com-
mon gate amplifier).
FIGURE 2-3:
PARS
COMMON RF INPUT AND
OUTPUT PIN DIAGRAM
PA Regulator
(1.8V)
RX ON
PA
To
RFIO
Antenna
MRF89XA
The PA and the LNA front-ends in the MRF89XA, which
share the same Input/Output pin, are internally
matched to approximately 50Ω.
2.4 Filters and Amplifiers Block
2.4.1 INTERPOLATION FILTER
After digital-to-analog conversion during transmission,
both I and Q signals are smoothed by interpolation
filters. These low-pass filters the digitally generated
signal, and prevents the alias signals from entering the
modulators.
2.4.2 POWER AMPLIFIER
The Power Amplifier (PA) integrated in the MRF89XA
operates under a regulated voltage supply of 1.8V. The
external RF choke inductor is biased by an internal
regulator output made available on the PARS pin (pin
29). Therefore, the PA output power is consistent over
the power supply range. This is important for
applications which allows both predictable RF
performance and battery life.
An open collector output requires biasing using an
inductor as an RF choke. For the recommended PA
bias and matching circuit details see Section 4.4.2,
Suggested PA Biasing And Matching.
Note: Image rejection is achieved using a SAW
filter on the RF input.
The matching of the SAW filter depends on the SAW
filter selected. Many modern SAW filters have 50Ω
input and output, which simplifies matching for the
MRF89XA. This is demonstrated in the application
circuit. If the choice of SAW filter is different than 50Ω,
the required impedance match on the input and output
of the SAW filter will be needed.
2.4.3
LOW NOISE AMPLIFIER (WITH
FIRST MIXER)
In Receive mode, the RFIO pin (pin 31) is connected to
a fixed gain, common-gate, Low Noise Amplifier (LNA).
The performance of this amplifier is such that the Noise
Figure (NF) of the receiver is estimated to be
approximately 7 dB.
The LNA has approximately 50Ω impedance, which
functions well with the proposed antenna (PCB/
Monopole) during signal transmission. The LNA is fol-
lowed by an internal RF band-pass filter.
LNA
© 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 15