MRF89XAM8A-I Datasheet, PDF (39/140 Pages) Microchip Technology – Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver

MRF89XA
REGISTER 2-14: FTXRXIREG: FIFO TRANSMIT AND RECEIVE INTERRUPT REQUEST
CONFIGURATION REGISTER (ADDRESS:0x0D) (POR:0x00) (CONTINUED)
bit 3
IRQ1TX: Transmit IRQ1 bit
This bit selects IRQ1 as source in Transmit mode.
If DMODE1:DMODE0 = 00 Î Continuous Mode (default):
x = DCLK
If DMODE1:DMODE0 = 01 Î Buffer Mode or 1x Î Packet Mode:
1 = TXDONE
0 = FIFOFULL (default)
bit 2
FIFOFULL: FIFO Full bit
This bit indicates FIFO Full through the IRQ source
1 = FIFO full
0 = FIFO not full
bit 1
FIFOEMPTY: FIFO Empty bit
This bit indicates FIFO empty through the IRQ source
1 = FIFO not Empty
0 = FIFO Empty
bit 0
FOVRRUN: FIFO Overrun Clear bit
This bit indicates if FIFO overrun occurred.
1 = FIFO Overrun occurred
0 = No FIFO Overrun occurred
Writing a ‘1’ for this bit clears flag and FIFO.
Note 1: This mode is also available in Stand-by mode.
2: PLREADY = Payload ready
3: ADRSMATCH = Address Match
© 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 39