MRF89XAM8A-I Datasheet, PDF (60/140 Pages) Microchip Technology – Ultra Low-Power, Integrated ISM Band Sub-GHz Transceiver

MRF89XA
3.3.6 POWER AMPLIFIER
3.3.6.1 Rise and Fall Time Control
In OOK mode, the PA ramp times can be accurately
controlled through the PARC<1:0> bits
(PACONREG<4:3>). These bits directly control the slew
rate of the PARS pin.
TABLE 3-2:
PARC<1:0>
00
01
10
11
POWER AMPLIFIER RISE/
FALL TIMES
t_PARS
t_PAOUT
(rise / fall)
3 µs
8.5 µs
15 µs
23 µs
2.5 / 2 µs
5 / 3 µs
10 / 6 µs
20 / 10 µs
FIGURE 3-4:
PA TIMING CONTROL
DATA
3.3.7 TRANSMIT MODE REGISTERS
The registers associated with Transmit mode are:
• GCONREG (Register 2-1)
• DMODREG (Register 2-2)
• FDEVREG (Register 2-3)
• BRSREG (Register 2-4)
• R1CREG (Register 2-7)
• P1CREG (Register 2-8)
• S1CREG (Register 2-9)
• R2CREG (Register 2-10)
• P2CREG (Register 2-11)
• S2CREG (Register 2-12)
• PACREG (Register 2-13)
• FTXRXIREG (Register 2-14)
• FTPRIREG (Register 2-15)
During the Transmit mode of MRF89XA, the Shift reg-
ister takes bytes from the FIFO and outputs them seri-
ally (MSb first) at the programmed bit rate to the
modulator. When the transmitter is enabled, it starts
sending out data from the Shift register with respect to
the set bit rate. After power-up and with the Transmit
registers enabled, the transmitter preloads the FIFO
with preambles before sending the actual data based
on the mode of operation. Figure 3-4 illustrates the PA
Control Timing.
PARS
[V]
95%
t_PARS
PA Output
Power
60 dB
t_{PA_OUT}
95%
t_PARS
60 dB
t_{PA_OUT}
DS70622C-page 60
Preliminary
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