LAN8700 Datasheet, PDF (8/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
3.0 PIN DESCRIPTION
This chapter describes the signals on each pin. When a lower case “n” is used at the beginning of the signal name, it
indicates that the signal is active low. For example, nRST indicates that the reset signal is active low.
3.1 I/O Signals
The following buffer types are shown in the TYPE column of the tables in this chapter.
•I
• IPD
•O
• OPD
• I/O
• IOPD
• IOPU
Input. Digital LVCMOS levels.
Input with internal pull-down. Digital LVCMOS levels.
Output. Digital LVCMOS levels.
Output with internal pull-down. Digital LVCMOS levels.
Input or Output. Digital LVCMOS levels.
Input or Output with internal pull-down. Digital LVCMOS levels.
Input or Output with internal pull-up. Digital LVCMOS levels.
Note:
• AI
• AO
The digital signals are not 5V tolerant.They are variable voltage from +1.6V to +3.6V.
Input. Analog levels.
Output. Analog levels.
TABLE 3-1: MII SIGNALS
Signal Name
TXD0
TXD1
TXD2
TXD3
nINT/
TX_ER/
TXD4
TX_EN
TX_CLK
Type
I
I
I
I
IOPU
IPD
O
Description
Transmit Data 0: Bit 0 of the 4 data bits that are accepted by the
PHY for transmission.
Transmit Data 1: Bit 1 of the 4 data bits that are accepted by the
PHY for transmission.
Transmit Data 2: Bit 2 of the 4 data bits that are accepted by the
PHY for transmission
Note: This signal should be grounded in RMII Mode.
Transmit Data 3: Bit 3 of the 4 data bits that are accepted by the
PHY for transmission.
Note: This signal should be grounded in RMII Mode
MII Transmit Error: When driven high, the 4B/5B encode process
substitutes the Transmit Error code-group (/H/) for the encoded
data word. This input is ignored in 10Base-T operation.
MII Transmit Data 4: In Symbol Interface (5B Decoding) mode,
this signal becomes the MII Transmit Data 4 line, the MSB of the
5-bit symbol code-group.
• This signal is not used in RMII Mode.
• This signal is mux’d with nINT
• See Section 4.10, "nINT/TX_ER/TXD4 Strapping," on page 24
for additional information on configuration/strapping options.
Transmit Enable: Indicates that valid data is presented on the
TXD[3:0] signals, for transmission. In RMII Mode, only TXD[1:0]
have valid data.
Transmit Clock: 25MHz in 100Base-TX mode. 2.5MHz in
10Base-T mode.
• This signal is not used in RMII Mode.
• For proper TXCLK operation, RX_ER and RX_DV must NOT
be driven high externally on a hardware reset or on a
LAN8700 power up.
DS00002260A-page 8
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