LAN8700 Datasheet, PDF (20/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
4.6 MAC Interface
The MII/RMII block is responsible for the communication with the controller. Special sets of hand-shake signals are used
to indicate that valid received/transmitted data is present on the 4 bit receive/transmit bus.
The device must be configured in MII or RMII mode. See Section 4.6.3, "MII vs. RMII Configuration," on page 21.
4.6.1 MII
The MII includes 16 interface signals:
• transmit data - TXD[3:0]
• transmit strobe - TX_EN
• transmit clock - TX_CLK
• transmit error - TX_ER/TXD4
• receive data - RXD[3:0]
• receive strobe - RX_DV
• receive clock - RX_CLK
• receive error - RX_ER/RXD4
• collision indication - COL
• carrier sense - CRS
In MII mode, on the transmit path, the PHY drives the transmit clock, TX_CLK, to the controller. The controller synchro-
nizes the transmit data to the rising edge of TX_CLK. The controller drives TX_EN high to indicate valid transmit data.
The controller drives TX_ER high when a transmit error is detected.
On the receive path, the PHY drives both the receive data, RXD[3:0], and the RX_CLK signal. The controller clocks in
the receive data on the rising edge of RX_CLK when the PHY drives RX_DV high. The PHY drives RX_ER high when
a receive error is detected.
4.6.2 RMII
The Microchip LAN8700/LAN8700i supports the low pin count Reduced Media Independent Interface (RMII) intended
for use between Ethernet PHYs and Switch ASICs. Under IEEE 802.3, an MII comprised of 16 pins for data and control
is defined. In devices incorporating many MACs or PHY interfaces such as switches, the number of pins can add sig-
nificant cost as the port counts increase. The management interface (MDIO/MDC) is identical to MII. The RMII interface
has the following characteristics:
• It is capable of supporting 10Mb/s and 100Mb/s data rates
• A single clock reference is sourced from the MAC to PHY (or from an external source)
• It provides independent 2 bit wide (di-bit) transmit and receive data paths
• It uses LVCMOS signal levels, compatible with common digital CMOS ASIC processes
The RMII includes 6 interface signals with one of the signals being optional:
• transmit data - TXD[1:0]
• transmit strobe - TX_EN
• receive data - RXD[1:0]
• receive error - RX_ER (Optional)
• carrier sense - CRS_DV
• Reference Clock - CLKIN/XTAL1 (RMII references usually define this signal as REF_CLK)
4.6.2.1 Reference Clock
The Reference Clock - CLKIN, is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN,
TXD[1:0], and RX_ER. The Reference Clock is sourced by the MAC or an external source. Switch implementations may
choose to provide REF_CLK as an input or an output depending on whether they provide a REF_CLK output or rely on
an external clock distribution device.
The “Reference Clock” frequency must be 50 MHz ± 50 ppm with a duty cycle between 40% and 60% inclusive. The
Microchip LAN8700/LAN8700i uses the “Reference Clock” as the network clock such that no buffering is required on
the transmit data path. The Microchip LAN8700/LAN8700i will recover the clock from the incoming data stream, the
receiver will account for differences between the local REF_CLK and the recovered clock through use of sufficient elas-
DS00002260A-page 20
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