LAN8700 Datasheet, PDF (56/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
6.5 Reset Timing
FIGURE 6-10:
RESET TIMING DIAGRAM
nRST
Configuration
Signals
Output drive
T _11.1
T_11.2
T _11.3
T _11.4
TABLE 6-11: RESET TIMING VALUES
Parameter
Description
MIN
T11.1
T11.2
T11.3
T11.4
Reset Pulse Width
100
Configuration input setup to nRST 200
rising
Configuration input hold after
2
nRST rising
Output Drive after nRST rising
3
TYP MAX
800
Units
us
ns
Notes
ns
ns 20 clock cycles for 25
MHz clock
- or -
40 clock cycles for
50MHz clock
DS00002260A-page 56
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