LAN8700 Datasheet, PDF (40/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
TABLE 5-43:
Address
29.1
29.0
REGISTER 29 - INTERRUPT SOURCE FLAGS (CONTINUED)
Name
Description
INT1
1 = Auto-Negotiation Page Received
0 = not source of interrupt
Reserved
Ignore on read.
Mode
RO/
LH
RO/
LH
Default
X
0
TABLE 5-44:
Address
30.15:8
30.7:1
30.0
REGISTER 30 - INTERRUPT MASK
Name
Description
Reserved
Mask Bits
Reserved
Write as 0; ignore on read.
1 = interrupt source is enabled
0 = interrupt source is masked
Write as 0; ignore on read
Mode
RO
RW
RO
Default
0
0
0
TABLE 5-45: REGISTER 31 - PHY SPECIAL CONTROL/STATUS
Address
Name
Description
31.15:13
31.12
31.11:10
31.9:7
31.6
31.5
31.4:2
31.1
31.0
Reserved
Autodone
Reserved
Reserved
Enable 4B5B
Reserved
Speed Indication
Reserved
Scramble Disable
Write as 0, ignore on read.
Auto-negotiation done indication:
0 = Auto-negotiation is not done or disabled (or not
active)
1 = Auto-negotiation is done
Note: This is a duplicate of register 1.5, however
reads to register 31 do not clear status bits.
Write as 0, ignore on Read.
Write as 0, ignore on Read.
0 = Bypass encoder/decoder.
1 = enable 4B5B encoding/decoding.
MAC Interface must be configured in MII mode.
Write as 0, ignore on Read.
HCDSPEED value:
[001]=10Mbps Half-duplex
[101]=10Mbps Full-duplex
[010]=100Base-TX Half-duplex
[110]=100Base-TX Full-duplex
Write as 0; ignore on Read
0 = enable data scrambling
1 = disable data scrambling,
Mode
RW
RO
RW
RW
RW
RW
RO
RW
RW
Default
0
0
XX
0
1
0
XXX
0
0
5.3 Interrupt Management
The Management interface supports an interrupt capability that is not a part of the IEEE 802.3 specification. It generates
an active low asynchronous interrupt signal on the nINT output whenever certain events are detected as setup by the
Interrupt Mask Register 30.
The Interrupt system on the Microchip LAN8700/8700I has two modes, a Primary Interrupt mode and an Alternative
Interrupt mode. Both systems will assert the nINT pin low when the corresponding mask bit is set, the difference is how
they de-assert the output interrupt signal nINT.
The Primary interrupt mode is the default interrupt mode after a power-up or hard reset, the Alternative interrupt mode
would need to be setup again after a power-up or hard reset.
5.3.1 PRIMARY INTERRUPT SYSTEM
bit The Primary Interrupt system is the default interrupt mode, (Bit 17.6 = ‘0’). The Primary Interrupt System is always
selected after power-up or hard reset.
DS00002260A-page 40
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