LAN8700 Datasheet, PDF (5/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
FIGURE 1-2:
LAN8700/LAN8700I ARCHITECTURAL OVERVIEW
MODE0
MODE1
MODE2
nRST
MII
MODE Control
SMI
Auto-
Negotiation
Management
Control
10M Tx
Logic
10M
Transmitter
Transmit Section
100M Tx
Logic
100M
Transmitter
TXD[0..3]
TX_EN
TX_ER
TX_CLK
RXD[0..3]
RX_DV
RX_ER
RX_CLK
CRS
COL/CRS_DV
MDC
MDIO
100M Rx
Logic
DSP System:
Clock
Data Recovery
Equalizer
Receive Section
Analog-to-
Digital
100M PLL
10M Rx
Logic
Squelch &
Filters
10M PLL
HP Auto-MDIX
TXP / TXN
RXP / RXN
MDIX
Control
PLL
PHY
Address
Latches
Interrupt
Generator
LED Circuitry
Central
Bias
XTAL1
XTAL2
nINT
PHYAD[0..4]
SPEED100
LINK
ACTIVITY
FDUPLEX
 2007-2016 Microchip Technology Inc.
DS00002260A-page 5