LAN8700 Datasheet, PDF (34/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
5.1 SMI Register Mapping
The following registers are supported (register numbers are in decimal):
TABLE 5-29: SMI REGISTER MAPPING
Register #
Description
0
Basic Control Register
1
Basic Status Register
2
PHY Identifier 1
3
PHY Identifier 2
4
Auto-Negotiation Advertisement Register
5
Auto-Negotiation Link Partner Ability Register
6
Auto-Negotiation Expansion Register
16
Silicon Revision Register
17
Mode Control/Status Register
18
Special Modes
20
Reserved
21
Reserved
22
Reserved
23
Reserved
26
Symbol Error Counter Register
27
Control / Status Indication Register
28
Special internal testability controls
29
Interrupt Source Register
30
Interrupt Mask Register
31
PHY Special Control/Status Register
5.2 SMI Register Format
The mode key is as follows:
• RW = Read/write,
• SC = Self clearing,
• WO = Write only,
• RO = Read only,
• LH = Latch high, clear on read of register,
• LL = Latch low, clear on read of register,
• NASR = Not Affected by Software Reset
• X = Either a 1 or 0.
Group
Basic
Basic
Extended
Extended
Extended
Extended
Extended
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
Vendor-specific
DS00002260A-page 34
 2007-2016 Microchip Technology Inc.