LAN8700 Datasheet, PDF (15/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
TABLE 4-1: 4B/5B CODE TABLE
Code Group
SYM
Receiver Interpretation
Transmitter Interpretation
11110
0
01001
1
10100
2
10101
3
01010
4
01011
5
01110
6
01111
7
0
0000
DATA
0
0000
DATA
1
0001
1
0001
2
0010
2
0010
3
0011
3
0011
4
0100
4
0100
5
0101
5
0101
6
0110
6
0110
7
0111
7
0111
10010
10011
10110
10111
11010
11011
11100
11101
11111
8
8
9
9
A
A
B
B
C
C
D
D
E
E
F
F
I
IDLE
1000
1001
1010
1011
1100
1101
1110
1111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
Sent after /T/R until TX_EN
11000
10001
01101
00111
00100
00110
11001
00000
00001
J
First nibble of SSD, translated to “0101” Sent for rising TX_EN
following IDLE, else RX_ER
K
Second nibble of SSD, translated to
“0101” following J, else RX_ER
Sent for rising TX_EN
T
First nibble of ESD, causes de-assertion Sent for falling TX_EN
of CRS if followed by /R/, else assertion of
RX_ER
R Second nibble of ESD, causes
Sent for falling TX_EN
deassertion of CRS if following /T/, else
assertion of RX_ER
H Transmit Error Symbol
Sent for rising TX_ER
V
INVALID, RX_ER if during RX_DV
INVALID
V
INVALID, RX_ER if during RX_DV
INVALID
V
INVALID, RX_ER if during RX_DV
INVALID
V
INVALID, RX_ER if during RX_DV
INVALID
00010
00011
00101
01000
01100
10000
V
INVALID, RX_ER if during RX_DV
V
INVALID, RX_ER if during RX_DV
V
INVALID, RX_ER if during RX_DV
V
INVALID, RX_ER if during RX_DV
V
INVALID, RX_ER if during RX_DV
V
INVALID, RX_ER if during RX_DV
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
4.2.3 SCRAMBLING
Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large narrow-band
peaks. Scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire
channel bandwidth. This uniform spectral density is required by FCC regulations to prevent excessive EMI from being
radiated by the physical wiring.
The seed for the scrambler is generated from the PHY address, PHYAD[4:0], ensuring that in multiple-PHY applications,
such as repeaters or switches, each PHY will have its own scrambler sequence.
The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.
 2007-2016 Microchip Technology Inc.
DS00002260A-page 15