LAN8700 Datasheet, PDF (43/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
5.4.4 LINK INTEGRITY TEST
The LAN8700/LAN8700i performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link Monitor state
diagram. The link status is multiplexed with the 10Mbps link status to form the reportable link status bit in Serial Man-
agement Register 1, and is driven to the LINK LED.
The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the ANSI X3.263 TP-
PMD standard, to the Link Monitor state-machine, using internal signal called DATA_VALID. When DATA_VALID is
asserted the control logic moves into a Link-Ready state, and waits for an enable from the Auto Negotiation block. When
received, the Link-Up state is entered, and the Transmit and Receive logic blocks become active. Should Auto Negoti-
ation be disabled, the link integrity logic moves immediately to the Link-Up state, when the DATA_VALID is asserted.
Note that to allow the line to stabilize, the link integrity logic will wait a minimum of 330 sec from the time DATA_VALID
is asserted until the Link-Ready state is entered. Should the DATA_VALID input be negated at any time, this logic will
immediately negate the Link signal and enter the Link-Down state.
When the 10/100 digital block is in 10Base-T mode, the link status is from the 10Base-T receiver logic.
5.4.5 POWER-DOWN MODES
There are 2 power-down modes for the Phy:
5.4.5.1 General Power-Down
This power-down is controlled by register 0, bit 11. In this mode the entire PHY, except the management interface, is
powered-down and stays in that condition as long as bit 0.11 is HIGH. When bit 0.11 is cleared, the PHY powers up and
is automatically reset.
5.4.5.2 Energy Detect Power-Down
This power-down mode is activated by setting bit 17.13 to 1. In this mode when no energy is present on the line the PHY
is powered down, except for the management interface, the SQUELCH circuit and the ENERGYON logic. The ENER-
GYON logic is used to detect the presence of valid energy from 100Base-TX, 10Base-T, or Auto-negotiation signals
In this mode, when the ENERGYON signal is low, the PHY is powered-down, and nothing is transmitted. When energy
is received - link pulses or packets - the ENERGYON signal goes high, and the PHY powers-up. It automatically resets
itself into the state it had prior to power-down, and asserts the nINT interrupt if the ENERGYON interrupt is enabled.
The first and possibly the second packet to activate ENERGYON may be lost.
When 17.13 is low, energy detect power-down is disabled.
5.4.6 RESET
The PHY has 3 reset sources:
Hardware reset (HWRST): connected to the nRST input. At power up, nRST must not go high until after the VDDIO
and VDD_CORE supplies are stable, as shown in Figure 5-1.
To initiate a hardware reset, nRST must be held LOW for at least 100 us to ensure that the Phy is properly reset, as
shown in Figure 6-10.
During a Hardware reset, an external clock must be supplied to the CLKIN signal.
FIGURE 5-1:
RESET TIMING DIAGRAM
3.3V
1.8V
0V
VDD33 Starts
VDD_CORE Starts
nRST Released
 2007-2016 Microchip Technology Inc.
DS00002260A-page 43