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| LAN8700 Datasheet, PDF (45/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint | |||
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LAN8700/LAN8700i
FIGURE 5-2:
NEAR-END LOOPBACK BLOCK DIAGRAM
10/100
Ethernet
MAC
TXD
RXD
Digital
X TX
X RX
Analog
XFMR
CAT-5
Ethernet Transceiver
5.4.8.2 Far Loopback
Far loopback is a special test mode for MDI (analog) loopback as indicated by the blue arrows in Figure 5-3. The far
loopback mode is enabled by setting bit register 17 bit 9 to logic one. In this mode, data that is received from the link
partner on the MDI is looped back out to the link partner. The digital interface signals on the local MAC interface are
isolated.
Note: This special test mode is only available when operating in RMII mode.
FIGURE 5-3:
FAR LOOPBACK BLOCK DIAGRAM
Far-end system
10/100
Ethernet
MAC
TXD X
RXDX
Digital
Analog
TX
XFMR
RX
CAT-5
Link
Partner
Ethernet Transceiver
5.4.8.3 Connector Loopback
The LAN8700/LAN8700i maintains reliable transmission over very short cables, and can be tested in a connector loop-
back as shown in Figure 5-4. An RJ45 loopback cable can be used to route the transmit signals an the output of the
transformer back to the receiver inputs, and this loopback will work at both 10 and 100.
ï£ 2007-2016 Microchip Technology Inc.
DS00002260A-page 45
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