LAN8700 Datasheet, PDF (23/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
Writing register 4 bits [8:5] allows software control of the capabilities advertised by the PHY. Writing register 4 does not
automatically re-start auto-negotiation. Register 0, bit 9 must be set before the new abilities will be advertised. Auto-
negotiation can also be disabled via software by clearing register 0, bit 12.
The LAN8700/LAN8700i does not support “Next Page” capability.
4.7.1 PARALLEL DETECTION
If the LAN8700/LAN8700i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected), it is
able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case
the link is presumed to be Half Duplex per the IEEE standard. This ability is known as “Parallel Detection.” This feature
ensures interoperability with legacy link partners. If a link is formed via parallel detection, then bit 0 in register 6 is cleared
to indicate that the Link Partner is not capable of auto-negotiation. The controller has access to this information via the
management interface. If a fault occurs during parallel detection, bit 4 of register 6 is set.
Register 5 is used to store the Link Partner Ability information, which is coded in the received FLPs. If the Link Partner
is not auto-negotiation capable, then register 5 is updated after completion of parallel detection to reflect the speed capa-
bility of the Link Partner.
4.7.2 RE-STARTING AUTO-NEGOTIATION
Auto-negotiation can be re-started at any time by setting register 0, bit 9. Auto-negotiation will also re-start if the link is
broken at any time. A broken link is caused by signal loss. This may occur because of a cable break, or because of an
interruption in the signal transmitted by the Link Partner. Auto-negotiation resumes in an attempt to determine the new
link configuration.
If the management entity re-starts Auto-negotiation by writing to bit 9 of the control register, the LAN8700/LAN8700i will
respond by stopping all transmission/receiving operations. Once the break_link_timer is done, in the Auto-negotiation
state-machine (approximately 1200ms) the auto-negotiation will re-start. The Link Partner will have also dropped the
link due to lack of a received signal, so it too will resume auto-negotiation.
4.7.3 DISABLING AUTO-NEGOTIATION
Auto-negotiation can be disabled by setting register 0, bit 12 to zero. The device will then force its speed of operation
to reflect the information in register 0, bit 13 (speed) and register 0, bit 8 (duplex). The speed and duplex bits in register
0 should be ignored when auto-negotiation is enabled.
4.7.4 HALF VS. FULL DUPLEX
Half Duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect) protocol to handle net-
work traffic and collisions. In this mode, the carrier sense signal, CRS, responds to both transmit and receive activity.
In this mode, If data is received while the PHY is transmitting, a collision results.
In Full Duplex mode, the PHY is able to transmit and receive data simultaneously. In this mode, CRS responds only to
receive activity. The CSMA/CD protocol does not apply and collision detection is disabled.
4.8 HP Auto-MDIX
HP Auto-MDIX facilitates the use of CAT-3 (10 Base-T) or CAT-5 (100 Base-T) media UTP interconnect cable without
consideration of interface wiring scheme. If a user plugs in either a direct connect LAN cable, or a cross-over patch
cable, as shown in FIGURE 4-4: on page 24, the Microchip LAN8700/LAN8700i Auto-MDIX PHY is capable of config-
uring the TXP/TXN and RXP/RXN pins for correct transceiver operation.
The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX and TX line pairs
are interchangeable, special PCB design considerations are needed to accommodate the symmetrical magnetics and
termination of an Auto-MDIX design.
The Auto-MDIX function can be disabled through an internal register.
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DS00002260A-page 23