LAN8700 Datasheet, PDF (25/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
The RXD3/nINTSEL pin is latched on the rising edge of the nRST. The system designer must float the nINTSEL pin to
put the nINT/TX_ER/TXD4 pin into nINT mode or pull-low to VSS with an external resistor (see Table 4-3, “Boot Strap-
ping Configuration Resistors,” on page 25) to set the device in TX_ER/TXD4 mode. The default setting is to float the pin
high for nINT mode.
4.11 PHY Address Strapping and LED Output Polarity Selection
The PHY ADDRESS bits are latched on the rising edge of the internal reset (nRESET). The 5-bit address word[0:4] is
input on the PHYAD[0:4] pins. The default setting is all high 5'b1_1111.
The address lines are strapped as defined in the diagram below. The LED outputs will automatically change polarity
based on the presence of an external pull-down resistor. If the LED pin is pulled high (by an internal 100K pull-up resis-
tor) to select a logical high PHY address, then the LED output will be active low. If the LED pin is pulled low (by an exter-
nal pull-down resistor (see Table 4-3, “Boot Strapping Configuration Resistors,” on page 25) to select a logical low PHY
address, the LED output will then be an active high output.
To set the PHY address on the LED pins without LEDs or on the CRS pin, float the pin to set the address high or pull-
down the pin with an external resistor (see Table 4-3, “Boot Strapping Configuration Resistors,” on page 25) to GND to
set the address low. See Figure 4-5, "PHY Address Strapping on LEDs":
FIGURE 4-5:
PHY ADDRESS STRAPPING ON LEDS
Phy Address = 1
LED output = active low
VDD
Phy Address = 0
LED output = active high
LED1-LED4
~10K ohms
~270 ohms
LED1-LED4
~270 ohms
4.12 Variable Voltage I/O
The Digital I/O pins on the LAN8700/LAN8700i are variable voltage to take advantage of low power savings from shrink-
ing technologies. These pins can operate from a low I/O voltage of +1.8V-10% up to +3.3V+10%. Due to this low voltage
feature addition, the system designer needs to take consideration as for two aspects of their design. Boot strapping con-
figuration and I/O voltage stability.
4.12.1 BOOT STRAPPING CONFIGURATION
Due to a lower I/O voltage, a lower strapping resistor needs to be used to ensure the strapped configuration is latched
into the PHY device at power-on reset.
TABLE 4-3: BOOT STRAPPING CONFIGURATION RESISTORS
I/O Voltage
Pull-up/Pull-down Resistor
3.0 to 3.6
2.0 to 3.0
1.6 to 2.0
10k ohm resistor
7.5k ohm resistor
5k ohm resistor
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DS00002260A-page 25