LAN8700 Datasheet, PDF (4/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
1.0 GENERAL DESCRIPTION
The Microchip LAN8700/LAN8700i is a low-power, industrial temperature (LAN8700i), variable I/O voltage, analog inter-
face IC with HP Auto-MDIX support for high-performance embedded Ethernet applications. The LAN8700/LAN8700i
can be configured to operate on a single 3.3V supply utilizing an integrated 3.3V to 1.8V linear regulator. An option is
available to disable the linear regulator to optimize system designs that have a 1.8V power plane available.
1.1 Architectural Overview
The LAN8700/LAN8700i consists of an encoder/decoder, scrambler/descrambler, wave-shaping transmitter, output
driver, twisted-pair receiver with adaptive equalizer and baseline wander (BLW) correction, and clock and data recovery
functions. The LAN8700/LAN8700i can be configured to support either the Media Independent Interface (MII) or the
Reduced Media Independent Interface (RMII).
The LAN8700/LAN8700i is compliant with IEEE 802.3-2005 standards (MII Pins tolerant to 3.6V) and supports both
IEEE 802.3-2005 compliant and vendor-specific register functions. It contains a full-duplex 10-BASE-T/100BASE-TX
transceiver and supports 10-Mbps (10BASE-T) operation on Category 3 and Category 5 unshielded twisted-pair cable,
and 100-Mbps (100BASE-TX) operation on Category 5 unshielded twisted-pair cable.
FIGURE 1-1:
LAN8700/LAN8700I SYSTEM BLOCK DIAGRAM
10/ 100
Media
Access
Controller
( MAC)
or SOC
System Bus
MII/ RMII
LAN8700/
LAN8700i
Magnetics
LEDS/ GPIO
Ethernet
25 MHz(MII ) or 50 MHz( RMIII)
Crystal or External Clock
Hubs and switches with multiple integrated MACs and external PHYs can have a large pin count due to the high number
of pins needed for each MII interface. An increasing pin count causes increasing cost.
The RMII interface is intended for use on Switch based ASICs or other embedded solutions requiring minimal pincount
for ethernet connectivity. RMII requires only 6 pins for each MAC to PHY interface plus one common reference clock.
The MII requires 16 pins for each MAC to PHY interface.
The Microchip LAN8700/LAN8700i is capable of running in RMII mode. Please contact your Microchip sales represen-
tative for the latest RMII specification.
The LAN8700/LAN8700i referenced throughout this document applies to both the commercial temperature and indus-
trial temperature components. The LAN8700i refers to only the industrial temperature component.
DS00002260A-page 4
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