LAN8700 Datasheet, PDF (63/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
8.0 APPLICATION NOTES
8.1 Application Diagram
FIGURE 8-1:
SIMPLIFIED APPLICATION DIAGRAM (SEE Section 8.4, "Reference Designs")
VDD3.3
VDD3.3
Voltage
Regulator
12.4k 1%
MII/RMII
MAC
(Media Access Controller)
Host System
Integrated
Magnetics and RJ45 Jack
1
2
3
4
5
6
7
8
nINT/TX_ER/TXD4
1
MDC
2
CRS/PHYAD4
3
MDIO
4
nRST
5
TX_EN
6
VDD33
7
VDD_CORE
8
SPEED100/PHYAD0
9
LAN8700/LAN8700I
MII/RMII Ethernet PHY
36 Pin QFN
GND FLAG
27 TXD3
26 ^TXD2
25 ^VDDIO
24 TXD1
23 TXD0
22 TX_CLK
21 RX_ER/RXD4
20
RX_CLK/REGOFF
19 RX_DV
Speed100
FullDuplex ^R1
Activity
R2
Link
R3
R4
Variable
Voltage
IO Regulator
VDDIO
Note: R5 on the Crystal is used to control the crystal drive strength into the PHY clock generator. This resistance
can be fine tuned to meet the requirements of each crystal manufacturer.
 2007-2016 Microchip Technology Inc.
DS00002260A-page 63