LAN8700 Datasheet, PDF (41/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
bit To set an interrupt, set the corresponding mask bit in the interrupt Mask register 30 (see Table 5-46). Then when the
event to assert nINT is true, the nINT output will be asserted.
When the corresponding Event to De-Assert nINT is true, then the nINT will be de-asserted.
TABLE 5-46: INTERRUPT MANAGEMENT
Mask
Interrupt Source Flag
Interrupt Source
Event to Assert nINT Event to De-Assert nINT
30.7 29.7
ENERGYON
17.1
ENERGYON
Rising 17.1⁽5-2⁾
Falling 17.1 or
Reading register 29
30.6 29.6
Auto-Negotiation
1.5
Auto-Negotiate
complete
Complete
Rising 1.5
Falling 1.5 or
Reading register 29
30.5 29.5 Remote Fault Detected 1.4
Remote Fault
Rising 1.4
Falling 1.4, or
Reading register 1 or
Reading register 29
30.4 29.4
Link Down
1.2
Link Status
Falling 1.2
Reading register 1 or
Reading register 29
30.3 29.3 Auto-Negotiation LP 5.14
Acknowledge
Acknowledge
Rising 5.14
Falling 5.14 or
Read register 29
30.2 29.2 Parallel Detection Fault 6.4 Parallel Detection Fault
Rising 6.4
Falling 6.4 or
Reading register 6, or
Reading register 29 or
Re-Auto Negotiate or
Link down
30.1 29.1
Note 5-2
Auto-Negotiation Page 6.1
Received
Page Received
Rising 6.1
Falling of 6.1 or
Reading register 6, or
Reading register 29
Re-Auto Negotiate, or
Link Down.
If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high, nINT will
assert for 256 ms, approximately one second after ENERGYON goes low when the Cable is
unplugged. To prevent an unexpected assertion of nINT, the ENERGYON interrupt mask should
always be cleared as part of the ENERGYON interrupt service routine
Note:
The ENERGYON bit 17.1 is defaulted to a ‘1’ at the start of the signal acquisition process, therefore the
Interrupt source flag 29.7 will also read as a ‘1’ at power-up. If no signal is present, then both 17.1 and 29.7
will clear within a few milliseconds.
5.3.2 ALTERNATE INTERRUPT SYSTEM
The Alternative method is enabled by writing a ‘1’ to 17.6 (ALTINT).
To set an interrupt, set the corresponding bit of the in the Mask Register 30, (see Table 5-47).
To Clear an interrupt, either clear the corresponding bit in the Mask Register (30), this will de-assert the nINT output, or
Clear the Interrupt Source, and write a ‘1’ to the corresponding Interrupt Source Flag. Writing a ‘1’ to the Interrupt Source
Flag will cause the state machine to check the Interrupt Source to determine if the Interrupt Source Flag should clear or
stay as a ‘1’. If the Condition to De-Assert is true, then the Interrupt Source Flag is cleared, and the nINT is also de-
asserted. If the Condition to De-Assert is false, then the Interrupt Source Flag remains set, and the nINT remains
asserted.
For example 30.7 is set to ‘1’ to enable the ENERGYON interrupt. After a cable is plugged in, ENERGYON (17.1) goes
active and nINT will be asserted low.
To de-assert the nINT interrupt output, either.
1. Clear the ENERGYON bit (17.1), by removing the cable, then writing a ‘1’ to register 29.7.
- Or -
2. Clear the Mask bit 30.1 by writing a ‘0’ to 30.1.
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DS00002260A-page 41