LAN8700 Datasheet, PDF (38/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
TABLE 5-38: REGISTER 17 - MODE CONTROL/STATUS (CONTINUED)
Address
Name
Description
17.10
17.9
17.8:7
17.6
17.5:4
17.3
17.2
17.1
17.0
MDPREBP
FARLOOPBACK
Reserved
ALTINT
Reserved
PHYADBP
Force
Good Link Status
ENERGYON
Reserved
Management Data Preamble Bypass:
0 – detect SMI packets with Preamble
1 – detect SMI packets without preamble
Force the module to the FAR Loop Back mode, i.e. all
the received packets are sent back simultaneously (in
100Base-TX only). This bit is only active in RMII mode.
In this mode the user needs to supply a 50MHz clock
to the PHY. This mode works even if MII Isolate (0.10)
is set.
Write as 0, ignore on read.
Alternate Interrupt Mode.
0 = Primary interrupt system enabled (Default).
1 = Alternate interrupt system enabled.
See Section 5.3, "Interrupt Management," on page 40.
Write as 0, ignore on read.
1 = PHY disregards PHY address in SMI access write.
0 = normal operation;
1 = force 100TX- link active;
Note: This bit should be set only during lab testing
ENERGYON – indicates whether energy is detected on
the line (see Section 5.4.5.2, "Energy Detect Power-
Down," on page 43); it goes to “0” if no valid energy is
detected within 256ms. Reset to “1” by hardware reset,
unaffected by SW reset.
Write as 0. Ignore on read.
Mode
RW
RW
RW
RW
RW
RW
RW
RO
RW
Default
0
0
00
0
00
0
0
X
0
TABLE 5-39:
Address
18.15
18.14
18.13:8
18.7:5
18.4:0
REGISTER 18 - SPECIAL MODES
Name
Description
Reserved
MIIMODE
Reserved
Write as 0, ignore on read.
MII Mode: Reflects the mode of the digital interface:
0 – MII interface.
1 – RMII interface
Note: When writing to this register, the default value
of this bit must always be written back.
Write as 0, ignore on read.
MODE
PHY Mode of operation. Refer to Section 5.4.9.2, "Mode
Bus – MODE[2:0]," on page 46 for more details.
PHYAD
PHY Address.
The PHY Address is used for the SMI address and for
the initialization of the Cipher (Scrambler) key. Refer to
Section 5.4.9.1, "Physical Address Bus - PHYAD[4:0],"
on page 46 for more details.
Mode
RW
RW,
NASR
RW,
NASR
RW,
NASR
RW,
NASR
Default
0
Note 5-1
000000
XXX
EVB8700
default 111
PHYAD
EVB8700
default
11111
Note 5-1
The default value of this field is determined by the strapping of the COL/RMII/CRS_DV pin. Refer to
Section 4.6.3, "MII vs. RMII Configuration," on page 21 for additional information.
DS00002260A-page 38
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