LAN8700 Datasheet, PDF (24/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
FIGURE 4-4:
DIRECT CABLE CONNECTION VS. CROSS-OVER CABLE CONNECTION
4.9 Internal +1.8V Regulator Disable
One feature of the flexPWR technology is the ability to configure the internal 1.8V regulator off. When the regulator is
disabled, external 1.8V must be supplied to VDD_CORE. This makes it possible to reduce total system power, since an
external switching regulator with greater efficiency than the internal linear regulator may be used to provide the +1.8V
to the PHY circuitry.
4.9.1 DISABLE THE INTERNAL +1.8V REGULATOR
To disable the +1.8V internal regulator, a pullup strapping resistor (see Table 4-3, “Boot Strapping Configuration Resis-
tors,” on page 25) is connected from RXCLK/REGOFF to VDDIO. At power-on, after both VDDIO and VDDA are within
specification, the PHY will sample the RXCLK/REGOFF pin to determine if the internal regulator should turn on. If the
pin is sampled at a voltage greater than V_IH, then the internal regulator is disabled, and the system must supply +1.8V
to the VDD_CORE pin. The voltage at VDD33 must be at least 2.64V (0.8 * 3.3V) before voltage is applied to
VDD_CORE. As described in Section 4.9.2, when the RXCLK/REGOFF pin is left floating or connected to VSS, then
the internal regulator is enabled and the system does not supply +1.8V to the VDD_CORE pin.
When the +1.8V internal regulator is disabled, a 0.1uF capacitor must be added at the VDD_CORE pin and placed close
to the PHY to decouple the external power supply.
4.9.2 ENABLE THE INTERNAL +1.8V REGULATOR
The 1.8V for VDD_CORE is supplied by the on-chip regulator unless the PHY is configured for regulator off mode using
the RX_CLK/REGOFF pin as described in Section 4.9.1. By default, the internal +1.8V regulator is enabled when the
RXCLK/REGOFF pin is floating. As shown in Table 7-11, an internal pull-down resistor straps the regulator on if the
RXCLK/REGOFF pin is floating.
During VDDIO and VDDA power-on, if the RXCLK/REGOFF pin is sampled below V_IL, then the internal +1.8V regulator
will turn on and operate with power from the VDD33 pin.
When using the internal linear regulator, a 4.7uF bypass capacitor with ESR < 1ohm and a 0.1uF capacitor must always
be added to VDD_CORE and placed close to the PHY to ensure stability of the internal regulator.
4.10 nINT/TX_ER/TXD4 Strapping
The nINT, TX_ER, and TXD4 functions share a common pin. There are two functional modes for this pin, the
TX_ER/TXD4 mode and nINT (interrupt) mode. The RXD3/nINTSEL pin is used to select one of these two functional
modes.
DS00002260A-page 24
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