LAN8700 Datasheet, PDF (11/74 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint

LAN8700/LAN8700i
TABLE 3-4: BOOT STRAP CONFIGURATION INPUTS (Note 3-1)
Signal Name
Type
Description
CRS/
PHYAD4
FDUPLEX/
PHYAD3
ACTIVITY/
PHYAD2
LINK/
PHYAD1
SPEED100/
PHYAD0
RXD2/
MODE2
RXD1/
MODE1
RXD0/
MODE0
COL/
RMII/
CRS_DV
IOPU
IOPU
IOPU
IOPU
IOPU
IOPU
IOPU
IOPU
IOPD
PHY Address Bit 4: set the default address of the PHY. This
signal is mux’d with CRS
Note: This signal is mux’d with CRS
PHY Address Bit 3: set the default address of the PHY.
Note: This signal is mux’d with FDUPLEX
PHY Address Bit 2: set the default address of the PHY.
Note: This signal is mux’d with ACTIVITY
PHY Address Bit 1: set the default address of the PHY.
Note: This signal is mux’d with LINK
PHY Address Bit 0: set the default address of the PHY.
Note: This signal is mux’d with SPEED100
PHY Operating Mode Bit 2: set the default MODE of the PHY.
See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 46, for the
MODE options.
Note: This signal is mux’d with RXD2
PHY Operating Mode Bit 1: set the default MODE of the PHY.
See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 46, for the
MODE options.
Note: This signal is mux’d with RXD1
PHY Operating Mode Bit 0: set the default MODE of the PHY.
See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 46, for the
MODE options.
Note: This signal is mux’d with RXD0
Digital Communication Mode: set the digital communications
mode of the PHY to RMII or MII. This signal is muxed with the
Collision signal (MII mode) and Carrier Sense/ receive Data Valid
(RMII mode)
• Float for MII mode.
• Pull up with a resistor to VDDIO for RMII mode (see Table 4-3,
“Boot Strapping Configuration Resistors,” on page 25)
RXD3/
nINTSEL
IOPU
nINT pin mode select: set the mode of pin 1.
• Default, left floating pin 1 is nINT, active low interrupt output.
• For nINT mode, tie nINT/TXD4/TXER to VDDIO with a resistor
(see Table 4-3, “Boot Strapping Configuration Resistors,” on
page 25).
• Pulled to VSS by a resistor, (see Table 4-3, “Boot Strapping
Configuration Resistors,” on page 25) pin 1 is TX_ER/TXD4,
Transmit Error or Transmit data 4 (5B mode).
• For TXD4/TXER mode, do not tie nINT/TXD4/TXER to VDDIO
or Ground.
Note 3-1 On nRST transition high, the PHY latches the state of the configuration pins in this table.
 2007-2016 Microchip Technology Inc.
DS00002260A-page 11